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In the context of porting applications to SVM, the Xe GT statistics are used by application developers to validate expected behavior such as proper alignment, page fault count and migrations. As those statistics are made for kernel developers, they assume good understanding of driver internals, which is not always the case on the application side. Therefore, this commit documents the usage of GT statistics and clarifies the meaning of identifiers which correspond to the values exposed via debugfs. Documentation is close to identifiers declaration to make it easier to maintain when adding new entries in the future. v2: Fix page reclaim list (PRL) entries (Matthew Brost) Assisted-by: GitHub Copilot:claude-sonnet-4.6 Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://lore.kernel.org/r/20260327202749.222794-1-francois.dugast@intel.com Signed-off-by: Francois Dugast <francois.dugast@intel.com>
204 lines
6.8 KiB
C
204 lines
6.8 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "xe_device.h"
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#include "xe_gt_stats.h"
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/**
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* DOC: Xe GT Statistics
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*
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* Overview
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* ========
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*
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* The Xe driver exposes per-GT statistics through the debugfs filesystem at::
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*
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* /sys/kernel/debug/dri/<device>/gt<id>/stats
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*
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* This interface requires the kernel to be built with ``CONFIG_DEBUG_FS=y``.
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*
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* Reading statistics
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* ==================
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*
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* Reading the file prints all available statistics, one per line, in
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* ``name: value`` format::
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*
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* $ cat /sys/kernel/debug/dri/0/gt0/stats
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* svm_pagefault_count: 0
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* tlb_inval_count: 1234
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* ...
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*
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* All values are 64-bit unsigned integers aggregated across all CPUs.
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* Counters accumulate since the driver was loaded or since the last explicit
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* reset. Timing counters use microseconds as their unit; data volume counters
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* use KiB.
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*
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* Resetting statistics
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* ====================
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*
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* Writing a boolean true value to the file resets all counters to zero::
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*
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* echo 1 > /sys/kernel/debug/dri/0/gt0/stats
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*
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* Any value accepted by ``kstrtobool()`` (e.g. ``1``, ``y``, ``yes``,
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* ``on``) triggers the reset. Resetting while the GPU is active may yield
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* unpredictable intermediate values; it is recommended to reset only when
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* the GPU is idle.
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*/
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static void xe_gt_stats_fini(struct drm_device *drm, void *arg)
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{
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struct xe_gt *gt = arg;
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free_percpu(gt->stats);
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}
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/**
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* xe_gt_stats_init() - Initialize GT statistics
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* @gt: GT structure
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*
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* Allocate per-CPU GT statistics. Using per-CPU stats allows increments
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* to occur without cross-CPU atomics.
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*
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* Return: 0 on success, -ENOMEM on failure.
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*/
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int xe_gt_stats_init(struct xe_gt *gt)
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{
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gt->stats = alloc_percpu(struct xe_gt_stats);
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if (!gt->stats)
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return -ENOMEM;
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return drmm_add_action_or_reset(>_to_xe(gt)->drm, xe_gt_stats_fini,
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gt);
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}
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/**
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* xe_gt_stats_incr - Increments the specified stats counter
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* @gt: GT structure
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* @id: xe_gt_stats_id type id that needs to be incremented
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* @incr: value to be incremented with
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*
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* Increments the specified stats counter.
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*/
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void xe_gt_stats_incr(struct xe_gt *gt, const enum xe_gt_stats_id id, int incr)
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{
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if (id >= __XE_GT_STATS_NUM_IDS)
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return;
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this_cpu_add(gt->stats->counters[id], incr);
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}
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#define DEF_STAT_STR(ID, name) [XE_GT_STATS_ID_##ID] = name
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static const char *const stat_description[__XE_GT_STATS_NUM_IDS] = {
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DEF_STAT_STR(SVM_PAGEFAULT_COUNT, "svm_pagefault_count"),
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DEF_STAT_STR(TLB_INVAL, "tlb_inval_count"),
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DEF_STAT_STR(SVM_TLB_INVAL_COUNT, "svm_tlb_inval_count"),
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DEF_STAT_STR(SVM_TLB_INVAL_US, "svm_tlb_inval_us"),
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DEF_STAT_STR(VMA_PAGEFAULT_COUNT, "vma_pagefault_count"),
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DEF_STAT_STR(VMA_PAGEFAULT_KB, "vma_pagefault_kb"),
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DEF_STAT_STR(INVALID_PREFETCH_PAGEFAULT_COUNT, "invalid_prefetch_pagefault_count"),
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DEF_STAT_STR(SVM_4K_PAGEFAULT_COUNT, "svm_4K_pagefault_count"),
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DEF_STAT_STR(SVM_64K_PAGEFAULT_COUNT, "svm_64K_pagefault_count"),
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DEF_STAT_STR(SVM_2M_PAGEFAULT_COUNT, "svm_2M_pagefault_count"),
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DEF_STAT_STR(SVM_4K_VALID_PAGEFAULT_COUNT, "svm_4K_valid_pagefault_count"),
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DEF_STAT_STR(SVM_64K_VALID_PAGEFAULT_COUNT, "svm_64K_valid_pagefault_count"),
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DEF_STAT_STR(SVM_2M_VALID_PAGEFAULT_COUNT, "svm_2M_valid_pagefault_count"),
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DEF_STAT_STR(SVM_4K_PAGEFAULT_US, "svm_4K_pagefault_us"),
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DEF_STAT_STR(SVM_64K_PAGEFAULT_US, "svm_64K_pagefault_us"),
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DEF_STAT_STR(SVM_2M_PAGEFAULT_US, "svm_2M_pagefault_us"),
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DEF_STAT_STR(SVM_4K_MIGRATE_COUNT, "svm_4K_migrate_count"),
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DEF_STAT_STR(SVM_64K_MIGRATE_COUNT, "svm_64K_migrate_count"),
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DEF_STAT_STR(SVM_2M_MIGRATE_COUNT, "svm_2M_migrate_count"),
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DEF_STAT_STR(SVM_4K_MIGRATE_US, "svm_4K_migrate_us"),
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DEF_STAT_STR(SVM_64K_MIGRATE_US, "svm_64K_migrate_us"),
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DEF_STAT_STR(SVM_2M_MIGRATE_US, "svm_2M_migrate_us"),
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DEF_STAT_STR(SVM_DEVICE_COPY_US, "svm_device_copy_us"),
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DEF_STAT_STR(SVM_4K_DEVICE_COPY_US, "svm_4K_device_copy_us"),
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DEF_STAT_STR(SVM_64K_DEVICE_COPY_US, "svm_64K_device_copy_us"),
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DEF_STAT_STR(SVM_2M_DEVICE_COPY_US, "svm_2M_device_copy_us"),
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DEF_STAT_STR(SVM_CPU_COPY_US, "svm_cpu_copy_us"),
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DEF_STAT_STR(SVM_4K_CPU_COPY_US, "svm_4K_cpu_copy_us"),
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DEF_STAT_STR(SVM_64K_CPU_COPY_US, "svm_64K_cpu_copy_us"),
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DEF_STAT_STR(SVM_2M_CPU_COPY_US, "svm_2M_cpu_copy_us"),
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DEF_STAT_STR(SVM_DEVICE_COPY_KB, "svm_device_copy_kb"),
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DEF_STAT_STR(SVM_4K_DEVICE_COPY_KB, "svm_4K_device_copy_kb"),
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DEF_STAT_STR(SVM_64K_DEVICE_COPY_KB, "svm_64K_device_copy_kb"),
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DEF_STAT_STR(SVM_2M_DEVICE_COPY_KB, "svm_2M_device_copy_kb"),
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DEF_STAT_STR(SVM_CPU_COPY_KB, "svm_cpu_copy_kb"),
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DEF_STAT_STR(SVM_4K_CPU_COPY_KB, "svm_4K_cpu_copy_kb"),
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DEF_STAT_STR(SVM_64K_CPU_COPY_KB, "svm_64K_cpu_copy_kb"),
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DEF_STAT_STR(SVM_2M_CPU_COPY_KB, "svm_2M_cpu_copy_kb"),
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DEF_STAT_STR(SVM_4K_GET_PAGES_US, "svm_4K_get_pages_us"),
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DEF_STAT_STR(SVM_64K_GET_PAGES_US, "svm_64K_get_pages_us"),
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DEF_STAT_STR(SVM_2M_GET_PAGES_US, "svm_2M_get_pages_us"),
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DEF_STAT_STR(SVM_4K_BIND_US, "svm_4K_bind_us"),
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DEF_STAT_STR(SVM_64K_BIND_US, "svm_64K_bind_us"),
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DEF_STAT_STR(SVM_2M_BIND_US, "svm_2M_bind_us"),
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DEF_STAT_STR(HW_ENGINE_GROUP_SUSPEND_LR_QUEUE_COUNT,
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"hw_engine_group_suspend_lr_queue_count"),
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DEF_STAT_STR(HW_ENGINE_GROUP_SKIP_LR_QUEUE_COUNT,
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"hw_engine_group_skip_lr_queue_count"),
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DEF_STAT_STR(HW_ENGINE_GROUP_WAIT_DMA_QUEUE_COUNT,
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"hw_engine_group_wait_dma_queue_count"),
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DEF_STAT_STR(HW_ENGINE_GROUP_SUSPEND_LR_QUEUE_US,
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"hw_engine_group_suspend_lr_queue_us"),
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DEF_STAT_STR(HW_ENGINE_GROUP_WAIT_DMA_QUEUE_US,
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"hw_engine_group_wait_dma_queue_us"),
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DEF_STAT_STR(PRL_4K_ENTRY_COUNT, "prl_4k_entry_count"),
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DEF_STAT_STR(PRL_64K_ENTRY_COUNT, "prl_64k_entry_count"),
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DEF_STAT_STR(PRL_2M_ENTRY_COUNT, "prl_2m_entry_count"),
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DEF_STAT_STR(PRL_ISSUED_COUNT, "prl_issued_count"),
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DEF_STAT_STR(PRL_ABORTED_COUNT, "prl_aborted_count"),
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};
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/**
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* xe_gt_stats_print_info - Print the GT stats
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* @gt: GT structure
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* @p: drm_printer where it will be printed out.
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*
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* This prints out all the available GT stats.
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*/
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int xe_gt_stats_print_info(struct xe_gt *gt, struct drm_printer *p)
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{
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enum xe_gt_stats_id id;
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for (id = 0; id < __XE_GT_STATS_NUM_IDS; ++id) {
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u64 total = 0;
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int cpu;
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for_each_possible_cpu(cpu) {
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struct xe_gt_stats *s = per_cpu_ptr(gt->stats, cpu);
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total += s->counters[id];
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}
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drm_printf(p, "%s: %lld\n", stat_description[id], total);
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}
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return 0;
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}
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/**
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* xe_gt_stats_clear() - Clear the GT stats
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* @gt: GT structure
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*
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* Clear (zero) all available GT stats. Note that if the stats are being
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* updated while this function is running, the results may be unpredictable.
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* Intended to be called on an idle GPU.
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*/
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void xe_gt_stats_clear(struct xe_gt *gt)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct xe_gt_stats *s = per_cpu_ptr(gt->stats, cpu);
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memset(s, 0, sizeof(*s));
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}
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}
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