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281a79f78d
Add register definitions for System Controller mailbox interface, including control, data, and protocol-related fields, along with base address and BAR configuration required by the driver. No functional changes. This patch introduces register definitions only. Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patch.msgid.link/20260327131837.2192929-11-anoop.c.vijay@intel.com
37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2026 Intel Corporation
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*/
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#ifndef _XE_SYSCTRL_REGS_H_
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#define _XE_SYSCTRL_REGS_H_
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#include "xe_regs.h"
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#define SYSCTRL_BASE_OFFSET 0xdb000
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#define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET)
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#define SYSCTRL_MAILBOX_INDEX 0x03
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#define SYSCTRL_BAR_LENGTH 0x1000
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#define SYSCTRL_MB_CTRL XE_REG(0x10)
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#define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31)
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#define SYSCTRL_MB_CTRL_IRQ REG_BIT(30)
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#define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29)
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#define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24)
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#define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16)
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#define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8)
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#define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0)
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#define SYSCTRL_MB_CTRL_CMD REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5)
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#define SYSCTRL_MB_DATA0 XE_REG(0x14)
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#define SYSCTRL_MB_DATA1 XE_REG(0x18)
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#define SYSCTRL_MB_DATA2 XE_REG(0x1c)
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#define SYSCTRL_MB_DATA3 XE_REG(0x20)
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#define SYSCTRL_FRAME_PHASE REG_BIT(24)
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#define SYSCTRL_FRAME_CURRENT_MASK REG_GENMASK(21, 16)
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#define SYSCTRL_FRAME_TOTAL_MASK REG_GENMASK(13, 8)
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#define SYSCTRL_FRAME_COMMAND_MASK REG_GENMASK(7, 0)
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#endif
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