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This is a from-scratch driver targeting Verisilicon DC-series display controllers, which feature self-identification functionality like their GC-series GPUs. Only DC8200 is being supported now, and only the main framebuffer is set up (as the DRM primary plane). Support for more DC models and more features is my further targets. As the display controller is delivered to SoC vendors as a whole part, this driver does not use component framework and extra bridges inside a SoC is expected to be implemented as dedicated bridges (this driver properly supports bridge chaining). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Tested-by: Han Gao <gaohan@iscas.ac.cn> Tested-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn
39 lines
743 B
C
39 lines
743 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me>
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*
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* Based on vs_dc_hw.h, which is:
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* Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
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*/
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#ifndef _VS_DC_H_
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#define _VS_DC_H_
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <drm/drm_device.h>
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#include "vs_hwdb.h"
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#define VSDC_MAX_OUTPUTS 2
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#define VSDC_RESET_COUNT 3
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struct vs_drm_dev;
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struct vs_crtc;
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struct vs_dc {
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struct regmap *regs;
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struct clk *core_clk;
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struct clk *axi_clk;
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struct clk *ahb_clk;
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struct clk *pix_clk[VSDC_MAX_OUTPUTS];
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struct reset_control_bulk_data rsts[VSDC_RESET_COUNT];
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struct vs_drm_dev *drm_dev;
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struct vs_chip_identity identity;
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};
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#endif /* _VS_DC_H_ */
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