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This is a from-scratch driver targeting Verisilicon DC-series display controllers, which feature self-identification functionality like their GC-series GPUs. Only DC8200 is being supported now, and only the main framebuffer is set up (as the DRM primary plane). Support for more DC models and more features is my further targets. As the display controller is delivered to SoC vendors as a whole part, this driver does not use component framework and extra bridges inside a SoC is expected to be implemented as dedicated bridges (this driver properly supports bridge chaining). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Tested-by: Han Gao <gaohan@iscas.ac.cn> Tested-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn
55 lines
2.0 KiB
C
55 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me>
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*
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* Based on vs_dc_hw.h, which is:
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* Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
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*/
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#ifndef _VS_BRIDGE_REGS_H_
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#define _VS_BRIDGE_REGS_H_
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#include <linux/bits.h>
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#define VSDC_DISP_PANEL_CONFIG(n) (0x1418 + 0x4 * (n))
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#define VSDC_DISP_PANEL_CONFIG_DE_EN BIT(0)
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#define VSDC_DISP_PANEL_CONFIG_DE_POL BIT(1)
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#define VSDC_DISP_PANEL_CONFIG_DAT_EN BIT(4)
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#define VSDC_DISP_PANEL_CONFIG_DAT_POL BIT(5)
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#define VSDC_DISP_PANEL_CONFIG_CLK_EN BIT(8)
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#define VSDC_DISP_PANEL_CONFIG_CLK_POL BIT(9)
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#define VSDC_DISP_PANEL_CONFIG_RUNNING BIT(12)
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#define VSDC_DISP_PANEL_CONFIG_GAMMA BIT(13)
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#define VSDC_DISP_PANEL_CONFIG_YUV BIT(16)
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#define VSDC_DISP_DPI_CONFIG(n) (0x14B8 + 0x4 * (n))
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#define VSDC_DISP_DPI_CONFIG_FMT_MASK GENMASK(2, 0)
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#define VSDC_DISP_DPI_CONFIG_FMT_RGB565 (0)
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#define VSDC_DISP_DPI_CONFIG_FMT_RGB666 (3)
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#define VSDC_DISP_DPI_CONFIG_FMT_RGB888 (5)
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#define VSDC_DISP_DPI_CONFIG_FMT_RGB101010 (6)
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#define VSDC_DISP_PANEL_START 0x1CCC
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#define VSDC_DISP_PANEL_START_RUNNING(n) BIT(n)
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#define VSDC_DISP_PANEL_START_MULTI_DISP_SYNC BIT(3)
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#define VSDC_DISP_DP_CONFIG(n) (0x1CD0 + 0x4 * (n))
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#define VSDC_DISP_DP_CONFIG_DP_EN BIT(3)
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#define VSDC_DISP_DP_CONFIG_FMT_MASK GENMASK(2, 0)
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#define VSDC_DISP_DP_CONFIG_FMT_RGB565 (0)
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#define VSDC_DISP_DP_CONFIG_FMT_RGB666 (1)
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#define VSDC_DISP_DP_CONFIG_FMT_RGB888 (2)
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#define VSDC_DISP_DP_CONFIG_FMT_RGB101010 (3)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_MASK GENMASK(7, 4)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 (2 << 4)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 (4 << 4)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 (8 << 4)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 (10 << 4)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 (12 << 4)
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#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 (13 << 4)
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#define VSDC_DISP_PANEL_CONFIG_EX(n) (0x2518 + 0x4 * (n))
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#define VSDC_DISP_PANEL_CONFIG_EX_COMMIT BIT(0)
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#endif /* _VS_BRIDGE_REGS_H_ */
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