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91f4da826c
Expose the command doorbell register to userspace on a per-hardware context basis, enabling applications to notify the firmware of pending commands via doorbell writes. Introduce DRM_IOCTL_AMDXDNA_WAIT_CMD to allow userspace to wait for completion of individual commands. Co-developed-by: Hayden Laccabue <Hayden.Laccabue@amd.com> Signed-off-by: Hayden Laccabue <Hayden.Laccabue@amd.com> Signed-off-by: David Zhang <yidong.zhang@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20260505160936.3917732-5-lizhi.hou@amd.com
101 lines
3.2 KiB
C
101 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2026, Advanced Micro Devices, Inc.
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*/
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_device.h>
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#include "aie4_pci.h"
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#include "amdxdna_pci_drv.h"
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#define NPU3_MBOX_BAR 0
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#define NPU3_MBOX_BUFFER_BAR 2
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#define NPU3_MBOX_INFO_OFF 0x0
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#define NPU3_DOORBELL_BAR 2
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#define NPU3_DOORBELL_OFF 0x0
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/* PCIe BAR Index for NPU3 */
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#define NPU3_REG_BAR_INDEX 0
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#define NPU3_PSP_BAR_INDEX 4
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#define NPU3_SMU_BAR_INDEX 5
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#define MMNPU_APERTURE3_BASE 0x3810000
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#define MMNPU_APERTURE4_BASE 0x3B10000
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#define NPU3_PSP_BAR_BASE MMNPU_APERTURE3_BASE
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#define NPU3_SMU_BAR_BASE MMNPU_APERTURE4_BASE
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#define MPASP_C2PMSG_123_ALT_1 0x3810AEC
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#define MPASP_C2PMSG_156_ALT_1 0x3810B70
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#define MPASP_C2PMSG_157_ALT_1 0x3810B74
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#define MPASP_C2PMSG_73_ALT_1 0x3810A24
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#define MP1_C2PMSG_59_ALT_1 0x3B109EC
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#define MP1_C2PMSG_61_ALT_1 0x3B109F4
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#define MP1_C2PMSG_60_ALT_1 0x3B109F0
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static const struct amdxdna_fw_feature_tbl npu3_fw_feature_table[] = {
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{ .major = 5, .min_minor = 10 },
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{ 0 }
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};
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static const struct amdxdna_dev_priv npu3_dev_priv = {
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.npufw_path = "npu.dev.sbin",
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.certfw_path = "cert.dev.sbin",
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.mbox_bar = NPU3_MBOX_BAR,
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.mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
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.mbox_info_off = NPU3_MBOX_INFO_OFF,
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.doorbell_off = NPU3_DOORBELL_OFF,
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.psp_regs_off = {
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DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1),
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DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1),
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DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU3_PSP, MPASP_C2PMSG_157_ALT_1),
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DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1),
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DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU3_PSP, MPASP_C2PMSG_73_ALT_1),
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DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU3_PSP, MPASP_C2PMSG_123_ALT_1),
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DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU3_PSP, MPASP_C2PMSG_156_ALT_1),
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/* npu3 doesn't use 8th pwaitmode register */
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},
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.smu_regs_off = {
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DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU3_SMU, MP1_C2PMSG_59_ALT_1),
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DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1),
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DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU3_SMU, MMNPU_APERTURE4_BASE),
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DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU3_SMU, MP1_C2PMSG_60_ALT_1),
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DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU3_SMU, MP1_C2PMSG_61_ALT_1),
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},
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};
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static const struct amdxdna_dev_priv npu3_dev_vf_priv = {
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/* vf device does not load firmware */
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.mbox_bar = NPU3_MBOX_BAR,
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.mbox_rbuf_bar = NPU3_MBOX_BUFFER_BAR,
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.mbox_info_off = NPU3_MBOX_INFO_OFF,
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/* vf device does not have smu and psp */
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};
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const struct amdxdna_dev_info dev_npu3_pf_info = {
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.mbox_bar = NPU3_MBOX_BAR,
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.sram_bar = NPU3_MBOX_BUFFER_BAR,
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.psp_bar = NPU3_PSP_BAR_INDEX,
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.smu_bar = NPU3_SMU_BAR_INDEX,
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.default_vbnv = "RyzenAI-npu3-pf",
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.device_type = AMDXDNA_DEV_TYPE_PF,
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.dev_priv = &npu3_dev_priv,
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.fw_feature_tbl = npu3_fw_feature_table,
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.ops = &aie4_pf_ops,
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};
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const struct amdxdna_dev_info dev_npu3_vf_info = {
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.mbox_bar = NPU3_MBOX_BAR,
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.sram_bar = NPU3_MBOX_BUFFER_BAR,
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.doorbell_bar = NPU3_DOORBELL_BAR,
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.default_vbnv = "RyzenAI-npu3-vf",
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.device_type = AMDXDNA_DEV_TYPE_UMQ,
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.dev_priv = &npu3_dev_vf_priv,
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.fw_feature_tbl = npu3_fw_feature_table,
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.ops = &aie4_vf_ops,
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};
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