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NPU firmware requires a host-allocated work buffer for hardware contexts. Allocate a 4 MB host buffer and attach it to device during device init. Refactor aie2_alloc_msg_buffer() and aie2_free_msg_buffer() into common helpers by moving them to aie.c and renaming them to amdxdna_alloc_msg_buffer() and amdxdna_free_msg_buffer(), allowing both AIE2 and AIE4 to reuse the implementation. Signed-off-by: Nishad Saraf <nishads@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/all/20260505160936.3917732-7-lizhi.hou@amd.com/
168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2026, Advanced Micro Devices, Inc.
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*/
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#include <linux/errno.h>
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#include "aie.h"
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#include "amdxdna_mailbox_helper.h"
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#include "amdxdna_mailbox.h"
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#include "amdxdna_pci_drv.h"
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void aie_dump_mgmt_chann_debug(struct aie_device *aie)
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{
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struct amdxdna_dev *xdna = aie->xdna;
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XDNA_DBG(xdna, "i2x tail 0x%x", aie->mgmt_i2x.mb_tail_ptr_reg);
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XDNA_DBG(xdna, "i2x head 0x%x", aie->mgmt_i2x.mb_head_ptr_reg);
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XDNA_DBG(xdna, "i2x ringbuf 0x%x", aie->mgmt_i2x.rb_start_addr);
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XDNA_DBG(xdna, "i2x rsize 0x%x", aie->mgmt_i2x.rb_size);
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XDNA_DBG(xdna, "x2i tail 0x%x", aie->mgmt_x2i.mb_tail_ptr_reg);
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XDNA_DBG(xdna, "x2i head 0x%x", aie->mgmt_x2i.mb_head_ptr_reg);
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XDNA_DBG(xdna, "x2i ringbuf 0x%x", aie->mgmt_x2i.rb_start_addr);
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XDNA_DBG(xdna, "x2i rsize 0x%x", aie->mgmt_x2i.rb_size);
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XDNA_DBG(xdna, "x2i chann index 0x%x", aie->mgmt_chan_idx);
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XDNA_DBG(xdna, "mailbox protocol major 0x%x", aie->mgmt_prot_major);
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XDNA_DBG(xdna, "mailbox protocol minor 0x%x", aie->mgmt_prot_minor);
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}
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void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann)
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{
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struct amdxdna_dev *xdna = aie->xdna;
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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if (!*chann)
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return;
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xdna_mailbox_stop_channel(*chann);
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xdna_mailbox_free_channel(*chann);
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*chann = NULL;
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}
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int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg)
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{
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struct amdxdna_dev *xdna = aie->xdna;
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struct xdna_notify *hdl = msg->handle;
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int ret;
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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if (!aie->mgmt_chann)
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return -ENODEV;
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ret = xdna_send_msg_wait(xdna, aie->mgmt_chann, msg);
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if (ret == -ETIME)
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aie_destroy_chann(aie, &aie->mgmt_chann);
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if (!ret && *hdl->status) {
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XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x",
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msg->opcode, *hdl->data);
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ret = -EINVAL;
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}
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return ret;
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}
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int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor)
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{
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const struct amdxdna_fw_feature_tbl *feature;
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bool found = false;
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for (feature = aie->xdna->dev_info->fw_feature_tbl;
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feature->major; feature++) {
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if (feature->major != fw_major)
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continue;
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if (fw_minor < feature->min_minor)
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continue;
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if (feature->max_minor > 0 && fw_minor > feature->max_minor)
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continue;
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aie->feature_mask |= feature->features;
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/* firmware version matches one of the driver support entry */
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found = true;
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}
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return found ? 0 : -EOPNOTSUPP;
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}
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static void amdxdna_update_vbnv(struct amdxdna_dev *xdna,
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const struct amdxdna_rev_vbnv *tbl,
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u32 rev)
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{
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int i;
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for (i = 0; tbl[i].vbnv; i++) {
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if (tbl[i].revision == rev) {
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xdna->vbnv = tbl[i].vbnv;
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break;
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}
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}
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}
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void amdxdna_vbnv_init(struct amdxdna_dev *xdna)
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{
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const struct amdxdna_dev_info *info = xdna->dev_info;
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u32 rev;
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xdna->vbnv = info->default_vbnv;
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if (!info->ops->get_dev_revision || !info->rev_vbnv_tbl)
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return;
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if (info->ops->get_dev_revision(xdna, &rev))
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return;
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amdxdna_update_vbnv(xdna, info->rev_vbnv_tbl, rev);
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}
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int amdxdna_get_metadata(struct aie_device *aie,
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struct amdxdna_client *client,
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struct amdxdna_drm_get_info *args)
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{
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int ret = 0;
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u32 buf_sz;
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buf_sz = min(args->buffer_size, sizeof(aie->metadata));
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if (copy_to_user(u64_to_user_ptr(args->buffer), &aie->metadata, buf_sz))
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ret = -EFAULT;
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return ret;
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}
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void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size,
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dma_addr_t *dma_addr)
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{
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void *vaddr;
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int order;
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*size = max_t(u32, *size, SZ_8K);
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order = get_order(*size);
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if (order > MAX_PAGE_ORDER)
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return ERR_PTR(-EINVAL);
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*size = PAGE_SIZE << order;
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if (amdxdna_iova_on(xdna))
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return amdxdna_iommu_alloc(xdna, *size, dma_addr);
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vaddr = dma_alloc_noncoherent(xdna->ddev.dev, *size, dma_addr,
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DMA_FROM_DEVICE, GFP_KERNEL);
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if (!vaddr)
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return ERR_PTR(-ENOMEM);
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return vaddr;
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}
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void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size,
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void *cpu_addr, dma_addr_t dma_addr)
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{
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if (amdxdna_iova_on(xdna)) {
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amdxdna_iommu_free(xdna, size, cpu_addr, dma_addr);
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return;
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}
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dma_free_noncoherent(xdna->ddev.dev, size, cpu_addr, dma_addr, DMA_FROM_DEVICE);
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}
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