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d6b70b16b4
The special treatment of these counts is just adding extra code for no real value. The irq_stats mechanism allows to suppress output of counters, which should never happen by default and provides a mechanism to enable them for the rare case that they occur. Move the IOAPIC misrouted and the PIC/APIC error counts into irq_stats, mark them suppressed by default and update the sites which increment them. This changes the output format of 'ERR' and 'MIS' in case there are events to the regular per CPU display format and otherwise suppresses them completely. As a side effect this removes the arch_cpu_stat() mechanism from proc/stat which was only there to account for the error interrupts on x86 and missed to take the misrouted ones into account. Signed-off-by: Thomas Gleixner <tglx@kernel.org> Tested-by: Michael Kelley <mhklinux@outlook.com> Reviewed-by: Radu Rendec <radu@rendec.net> Link: https://patch.msgid.link/20260517194931.361942103@kernel.org
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_HARDIRQ_H
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#define _ASM_X86_HARDIRQ_H
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#include <linux/threads.h>
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enum irq_stat_counts {
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IRQ_COUNT_NMI,
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#ifdef CONFIG_X86_LOCAL_APIC
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IRQ_COUNT_APIC_TIMER,
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IRQ_COUNT_SPURIOUS,
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IRQ_COUNT_APIC_PERF,
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IRQ_COUNT_IRQ_WORK,
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IRQ_COUNT_ICR_READ_RETRY,
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IRQ_COUNT_X86_PLATFORM_IPI,
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#endif
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#ifdef CONFIG_SMP
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IRQ_COUNT_RESCHEDULE,
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IRQ_COUNT_CALL_FUNCTION,
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#endif
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IRQ_COUNT_TLB,
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#ifdef CONFIG_X86_THERMAL_VECTOR
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IRQ_COUNT_THERMAL_APIC,
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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IRQ_COUNT_THRESHOLD_APIC,
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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IRQ_COUNT_DEFERRED_ERROR,
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#endif
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#ifdef CONFIG_X86_MCE
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IRQ_COUNT_MCE_EXCEPTION,
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IRQ_COUNT_MCE_POLL,
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#endif
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#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
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IRQ_COUNT_HYPERVISOR_CALLBACK,
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#endif
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#if IS_ENABLED(CONFIG_HYPERV)
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IRQ_COUNT_HYPERV_REENLIGHTENMENT,
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IRQ_COUNT_HYPERV_STIMER0,
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#endif
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#if IS_ENABLED(CONFIG_KVM)
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IRQ_COUNT_POSTED_INTR,
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IRQ_COUNT_POSTED_INTR_NESTED,
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IRQ_COUNT_POSTED_INTR_WAKEUP,
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#endif
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#ifdef CONFIG_GUEST_PERF_EVENTS
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IRQ_COUNT_PERF_GUEST_MEDIATED_PMI,
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#endif
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#ifdef CONFIG_X86_POSTED_MSI
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IRQ_COUNT_POSTED_MSI_NOTIFICATION,
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#endif
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IRQ_COUNT_PIC_APIC_ERROR,
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#ifdef CONFIG_X86_IO_APIC
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IRQ_COUNT_IOAPIC_MISROUTED,
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#endif
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IRQ_COUNT_MAX,
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};
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typedef struct {
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#if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL)
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u8 kvm_cpu_l1tf_flush_l1d;
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#endif
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unsigned int counts[IRQ_COUNT_MAX];
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} ____cacheline_aligned irq_cpustat_t;
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DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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#ifdef CONFIG_X86_POSTED_MSI
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DECLARE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);
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#endif
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#define __ARCH_IRQ_STAT
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#define inc_irq_stat(index) this_cpu_inc(irq_stat.counts[IRQ_COUNT_##index])
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void irq_stat_inc_and_enable(enum irq_stat_counts which);
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#ifdef CONFIG_X86_LOCAL_APIC
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#define inc_perf_irq_stat() inc_irq_stat(APIC_PERF)
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#else
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#define inc_perf_irq_stat() do { } while (0)
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#endif
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extern void ack_bad_irq(unsigned int irq);
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#ifdef CONFIG_PROC_FS
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extern u64 arch_irq_stat_cpu(unsigned int cpu);
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#define arch_irq_stat_cpu arch_irq_stat_cpu
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#endif
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DECLARE_PER_CPU_CACHE_HOT(u16, __softirq_pending);
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#define local_softirq_pending_ref __softirq_pending
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#if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL)
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/*
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* This function is called from noinstr interrupt contexts
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* and must be inlined to not get instrumentation.
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*/
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static __always_inline void kvm_set_cpu_l1tf_flush_l1d(void)
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{
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__this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1);
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}
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static __always_inline void kvm_clear_cpu_l1tf_flush_l1d(void)
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{
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__this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 0);
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}
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static __always_inline bool kvm_get_cpu_l1tf_flush_l1d(void)
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{
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return __this_cpu_read(irq_stat.kvm_cpu_l1tf_flush_l1d);
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}
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#else /* !IS_ENABLED(CONFIG_KVM_INTEL) */
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static __always_inline void kvm_set_cpu_l1tf_flush_l1d(void) { }
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#endif /* IS_ENABLED(CONFIG_KVM_INTEL) */
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#endif /* _ASM_X86_HARDIRQ_H */
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