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87a451161f
On x86 SMP systems with the F00F bug present, do_clear_cpu_cap()
rightfully warns that the code clears the X86_BUG_F00F flag after
alternatives have been patched.
X86_BUG_F00F is first cleared in intel_workarounds() and then set for
the affected models. This sequence works fine on the BSP but on AP
bringup, where alternatives have already been patched and clearing the
flag there triggers the warning.
There is no technical reason for clearing the flag before setting it. It
is mainly an artifact of introducing the X86_BUG_F00F flag in
e2604b49e8 ("x86, cpu: Convert F00F bug detection").
Remove the unnecessary clearing of the flag.
While at it, remove the kernel notification and the surrounding logic to
inform the user about the workaround exactly once. If needed, the
presence of the F00F bug can be determined through /proc/cpuinfo.
Additionally, the F00F bug was the last remaining user of clear_cpu_bug().
With no users left, get rid of this helper as well.
[ bp: Massage commit message. ]
Co-developed-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://patch.msgid.link/20260528184826.3642051-1-sohil.mehta@intel.com
142 lines
4.0 KiB
C
142 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CPUFEATURE_H
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#define _ASM_X86_CPUFEATURE_H
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#include <asm/processor.h>
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#if defined(__KERNEL__) && !defined(__ASSEMBLER__)
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#include <asm/asm.h>
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#include <linux/bitops.h>
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#include <asm/alternative.h>
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#include <asm/cpufeaturemasks.h>
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enum cpuid_leafs
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{
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CPUID_1_EDX = 0,
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CPUID_8000_0001_EDX,
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CPUID_8086_0001_EDX,
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CPUID_LNX_1,
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CPUID_1_ECX,
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CPUID_C000_0001_EDX,
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CPUID_8000_0001_ECX,
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CPUID_LNX_2,
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CPUID_LNX_3,
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CPUID_7_0_EBX,
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CPUID_D_1_EAX,
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CPUID_LNX_4,
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CPUID_7_1_EAX,
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CPUID_8000_0008_EBX,
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CPUID_6_EAX,
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CPUID_8000_000A_EDX,
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CPUID_7_ECX,
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CPUID_LNX_6,
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CPUID_7_EDX,
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CPUID_8000_001F_EAX,
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CPUID_8000_0021_EAX,
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CPUID_LNX_5,
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NR_CPUID_WORDS,
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};
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extern const char * const x86_cap_flags[NCAPINTS*32];
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extern const char * const x86_power_flags[32];
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/*
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* In order to save room, we index into this array by doing
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* X86_BUG_<name> - NCAPINTS*32.
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*/
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extern const char * const x86_bug_flags[NBUGINTS*32];
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#define x86_bug_flag(flag) x86_bug_flags[flag]
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#define test_cpu_cap(c, bit) \
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arch_test_bit(bit, (unsigned long *)((c)->x86_capability))
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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test_cpu_cap(c, bit))
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#define this_cpu_has(bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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x86_this_cpu_test_bit(bit, cpu_info.x86_capability))
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/*
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* This is the default CPU features testing macro to use in code.
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*
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* It is for detection of features which need kernel infrastructure to be
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* used. It may *not* directly test the CPU itself. Use the cpu_has() family
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* if you want true runtime testing of CPU features, like in hypervisor code
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* where you are supporting a possible guest feature where host support for it
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* is not relevant.
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*/
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#define cpu_feature_enabled(bit) \
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(__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit))
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#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
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#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
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extern void setup_clear_cpu_cap(unsigned int bit);
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extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit);
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void check_cpufeature_deps(struct cpuinfo_x86 *c);
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#define setup_force_cpu_cap(bit) do { \
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\
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if (!boot_cpu_has(bit)) \
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WARN_ON(alternatives_patched); \
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\
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set_cpu_cap(&boot_cpu_data, bit); \
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set_bit(bit, (unsigned long *)cpu_caps_set); \
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} while (0)
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#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit)
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/*
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* Do not use an "m" constraint for [cap_byte] here: gcc doesn't know
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* that this is only used on a fallback path and will sometimes cause
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* it to manifest the address of boot_cpu_data in a register, fouling
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* the mainline (post-initialization) code.
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*/
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static __always_inline bool _static_cpu_has(u16 bit)
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{
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asm goto(ALTERNATIVE_TERNARY("jmp 6f", %c[feature], "", "jmp %l[t_no]")
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".pushsection .altinstr_aux,\"ax\"\n"
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"6:\n"
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ANNOTATE_DATA_SPECIAL "\n"
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" testb %[bitnum], %a[cap_byte]\n"
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" jnz %l[t_yes]\n"
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" jmp %l[t_no]\n"
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".popsection\n"
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: : [feature] "i" (bit),
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[bitnum] "i" (1 << (bit & 7)),
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[cap_byte] "i" (&((const char *)boot_cpu_data.x86_capability)[bit >> 3])
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: : t_yes, t_no);
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t_yes:
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return true;
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t_no:
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return false;
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}
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#define static_cpu_has(bit) \
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( \
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__builtin_constant_p(boot_cpu_has(bit)) ? \
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boot_cpu_has(bit) : \
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_static_cpu_has(bit) \
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)
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#define cpu_has_bug(c, bit) cpu_has(c, (bit))
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#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
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#define static_cpu_has_bug(bit) static_cpu_has((bit))
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#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
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#define boot_cpu_set_bug(bit) set_cpu_cap(&boot_cpu_data, (bit))
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#define MAX_CPU_FEATURES (NCAPINTS * 32)
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#define cpu_have_feature boot_cpu_has
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#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X"
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#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
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boot_cpu_data.x86_model
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#endif /* defined(__KERNEL__) && !defined(__ASSEMBLER__) */
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#endif /* _ASM_X86_CPUFEATURE_H */
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