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4ad04e7c7e
Adjust process management for both 32BIT and 64BIT, including: CPU context switching, FPU loading/restoring, process dumping and process tracing routines. Q: Why modify switch.S? A: LoongArch32 has no ldptr.d/stptr.d instructions, and asm offsets of thead_struct members are too large to be filled in the 12b immediate field of ld.w/st.w. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
95 lines
1.7 KiB
C
95 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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/*
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* Author: Hanlu Li <lihanlu@loongson.cn>
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* Huacai Chen <chenhuacai@loongson.cn>
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _UAPI_ASM_PTRACE_H
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#define _UAPI_ASM_PTRACE_H
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#include <linux/types.h>
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/*
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* For PTRACE_{POKE,PEEK}USR. 0 - 31 are GPRs,
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* 32 is syscall's original ARG0, 33 is PC, 34 is BADVADDR.
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*/
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#define GPR_BASE 0
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#define GPR_NUM 32
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#define GPR_END (GPR_BASE + GPR_NUM - 1)
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#define ARG0 (GPR_END + 1)
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#define PC (GPR_END + 2)
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#define BADVADDR (GPR_END + 3)
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#define NUM_FPU_REGS 32
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struct user_pt_regs {
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/* Main processor registers. */
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unsigned long regs[32];
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/* Original syscall arg0. */
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unsigned long orig_a0;
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/* Special CSR registers. */
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unsigned long csr_era;
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unsigned long csr_badv;
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unsigned long reserved[10];
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} __attribute__((aligned(8)));
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struct user_fp_state {
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__u64 fpr[32];
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__u64 fcc;
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__u32 fcsr;
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};
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struct user_lsx_state {
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/* 32 registers, 128 bits width per register. */
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__u64 vregs[32*2];
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};
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struct user_lasx_state {
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/* 32 registers, 256 bits width per register. */
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__u64 vregs[32*4];
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};
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struct user_lbt_state {
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__u64 scr[4];
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__u32 eflags;
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__u32 ftop;
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};
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struct user_watch_state {
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__u64 dbg_info;
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struct {
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#if __BITS_PER_LONG == 32
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__u32 addr;
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__u32 mask;
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#else
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__u64 addr;
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__u64 mask;
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#endif
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__u32 ctrl;
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__u32 pad;
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} dbg_regs[8];
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};
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struct user_watch_state_v2 {
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__u64 dbg_info;
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struct {
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#if __BITS_PER_LONG == 32
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__u32 addr;
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__u32 mask;
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#else
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__u64 addr;
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__u64 mask;
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#endif
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__u32 ctrl;
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__u32 pad;
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} dbg_regs[14];
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};
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#define PTRACE_SYSEMU 0x1f
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#define PTRACE_SYSEMU_SINGLESTEP 0x20
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#endif /* _UAPI_ASM_PTRACE_H */
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