mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-29 15:06:30 -04:00
0d8c113493
Pull crypto updates from Herbert Xu:
"API:
- Drop support for off-CPU cryptography in af_alg
- Document that af_alg is *always* slower
- Document the deprecation of af_alg
- Remove zero-copy support from skcipher and aead in af_alg
- Cap AEAD AD length to 0x80000000 in af_alg
- Free default RNG on module exit
Algorithms:
- Fix vli multiplication carry overflow in ecc
- Drop unused cipher_null crypto_alg
- Remove unused variants of drbg
- Use lib/crypto in drbg
- Use memcpy_from/to_sglist in authencesn
- Allow authenc(hmac(sha{256,384}),cts(cbc(aes))) in FIPS mode
- Disallow RSA PKCS#1 SHA-1 sig algs in FIPS mode
- Filter out async aead implementations at alloc in krb5
- Fix non-parallel fallback by rstoring callback in pcrypt
- Validate poly1305 template argument in chacha20poly1305
Drivers:
- Add sysfs PCI reset support to qat
- Add KPT support for GEN6 devices to qat
- Remove unused character device and ioctls from qat
- Add support for hw access via SMCC to mtk
- Remove prng support from crypto4xx
- Remove prng support from hisi-trng
- Remove prng support from sun4i-ss
- Remove prng support from xilinx-trng
- Remove loongson-rng
- Remove exynos-rng
Others:
- Remove support for AIO on sockets"
* tag 'v7.2-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (196 commits)
crypto: tegra - fix refcount leak in tegra_se_host1x_submit()
crypto: rng - Free default RNG on module exit
crypto: testmgr - allow authenc(hmac(sha{256,384}),cts(cbc(aes))) in FIPS mode
hwrng: jh7110 - fix refcount leak in starfive_trng_read()
crypto: atmel-ecc - drop dead code in atmel_ecdh_max_size
crypto: cavium/cpt - fix DMA cleanup using wrong loop index
crypto: marvell/octeontx - fix DMA cleanup using wrong loop index
MAINTAINERS: make myself the maintainer of the Qualcomm QCE driver
crypto: amcc - convert irq_of_parse_and_map to platform_get_irq
crypto: sun4i-ss - Remove insecure and unused rng_alg
hwrng: xilinx - Move xilinx-rng into drivers/char/hw_random/
crypto: xilinx-trng - Replace crypto_drbg_ctr_df() with HMAC-SHA512
crypto: xilinx-trng - Fix return value of xtrng_hwrng_trng_read()
crypto: xilinx-trng - Remove crypto_rng interface
crypto: exynos-rng - Remove exynos-rng driver
hwrng: hisi-trng - Move hisi-trng into drivers/char/hw_random/
crypto: hisi-trng - Remove crypto_rng interface
crypto: loongson - Remove broken and unused loongson-rng
crypto: crypto4xx - Remove insecure and unused rng_alg
crypto: qat - validate RSA CRT component lengths
...
113 lines
2.5 KiB
YAML
113 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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properties:
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compatible:
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items:
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- enum:
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- qcom,eliza-inline-crypto-engine
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- qcom,hawi-inline-crypto-engine
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- qcom,kaanapali-inline-crypto-engine
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- qcom,milos-inline-crypto-engine
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- qcom,qcs8300-inline-crypto-engine
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- qcom,sa8775p-inline-crypto-engine
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- qcom,sc7180-inline-crypto-engine
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- qcom,sc7280-inline-crypto-engine
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- qcom,sm8450-inline-crypto-engine
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- qcom,sm8550-inline-crypto-engine
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- qcom,sm8650-inline-crypto-engine
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- qcom,sm8750-inline-crypto-engine
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- const: qcom,inline-crypto-engine
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: core
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- const: iface
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power-domains:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,eliza-inline-crypto-engine
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- qcom,milos-inline-crypto-engine
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then:
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required:
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- power-domains
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- clock-names
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8550-gcc.h>
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crypto@1d88000 {
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compatible = "qcom,sm8550-inline-crypto-engine",
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"qcom,inline-crypto-engine";
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reg = <0x01d88000 0x8000>;
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clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>;
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clock-names = "core",
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"iface";
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power-domains = <&gcc UFS_PHY_GDSC>;
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operating-points-v2 = <&ice_opp_table>;
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ice_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-201500000 {
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opp-hz = /bits/ 64 <201500000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-403000000 {
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opp-hz = /bits/ 64 <403000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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...
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