Files
linux/include/uapi
Krishna Chaitanya Chundru 178af54a67 PCI: Add lane equalization register offsets
As per PCIe spec 6.0.1, add PCIe lane equalization register offset for
data rates 8.0 GT/s, 32.0 GT/s and 64.0 GT/s.

Also add a macro for defining data rate 64.0 GT/s physical layer capability
ID.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250328-preset_v6-v9-4-22cfa0490518@oss.qualcomm.com
2025-04-19 19:42:43 +05:30
..
2025-03-16 22:04:27 +11:00
2024-01-04 13:22:24 +00:00
2025-02-03 18:04:55 -05:00