Riana Tauro 0914c1e45d drm/xe/xe_gt_idle: add debugfs entry for powergating info ...

Coarse Powergating is a power saving technique where Render and Media
can be power-gated independently irrespective of the rest of the GT.

For debug purposes, it is useful to expose the powergating information.

v2: move to debugfs
    add details to commit message
    add per-slice status for media
    define reg bits in descending order (Matt Roper)

v3: fix return statement
    fix kernel-doc
    use loop for media slices
    use helper function for status (Michal)

v4: add pg prefix
    do not wake GT if in C6 (Badal)

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240906071126.28078-3-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

2024-09-06 12:13:30 -04:00

..

drm

drm/xe/xe_gt_idle: add debugfs entry for powergating info

2024-09-06 12:13:30 -04:00

host1x

driver core: have match() callback in struct bus_type take a const *

2024-07-03 15:16:54 +02:00

ipu-v3

Merge tag 'driver-core-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

2024-07-25 10:42:22 -07:00

trace

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vga

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Makefile

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