Sung Lee 06535a48e2 drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1 ...

[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-04-22 18:11:48 -04:00

..

drm

drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

2020-04-22 18:11:48 -04:00

host1x

Merge tag 'drm/tegra/for-5.6-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next

2020-02-07 12:22:30 +10:00

ipu-v3

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vga

vga: Fix Kconfig indentation

2019-11-20 17:40:32 +01:00

Makefile

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