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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-18 20:31:06 -04:00
a158fe7b0c
The platform name will be used in the topology name.
Fixes: d3df422f66 ("ASoC: SOF: Intel: add initial support for NVL-S")
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://patch.msgid.link/20260413060800.3156425-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2025 Intel Corporation
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/*
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* Hardware interface for audio DSP on NovaLake.
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*/
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#include <sound/hda_register.h>
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#include <sound/hda-mlink.h>
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#include <sound/sof/ipc4/header.h>
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#include "../ipc4-priv.h"
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#include "../ops.h"
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#include "hda.h"
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#include "hda-ipc.h"
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#include "../sof-audio.h"
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#include "mtl.h"
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#include "lnl.h"
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#include "ptl.h"
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#include "nvl.h"
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int sof_nvl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops)
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{
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/* Use PTL ops for NVL */
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return sof_ptl_set_ops(sdev, dsp_ops);
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};
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EXPORT_SYMBOL_NS(sof_nvl_set_ops, "SND_SOC_SOF_INTEL_NVL");
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const struct sof_intel_dsp_desc nvl_chip_info = {
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.cores_num = 4,
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.init_core_mask = BIT(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = MTL_DSP_REG_HFIPCXIDR,
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.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
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.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
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.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
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.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
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.rom_status_reg = LNL_DSP_REG_HFDSC,
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.rom_init_timeout = 300,
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.ssp_count = MTL_SSP_COUNT,
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.d0i3_offset = MTL_HDA_VS_D0I3C,
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.read_sdw_lcount = hda_sdw_check_lcount_ext,
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.check_sdw_irq = lnl_dsp_check_sdw_irq,
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.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
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.sdw_process_wakeen = hda_sdw_process_wakeen_common,
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.check_ipc_irq = mtl_dsp_check_ipc_irq,
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.cl_init = mtl_dsp_cl_init,
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.power_down_dsp = mtl_power_down_dsp,
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.disable_interrupts = lnl_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_ACE_4_0,
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.platform = "nvl",
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};
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const struct sof_intel_dsp_desc nvl_s_chip_info = {
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.cores_num = 2,
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.init_core_mask = BIT(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = MTL_DSP_REG_HFIPCXIDR,
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.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
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.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
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.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
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.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
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.rom_status_reg = LNL_DSP_REG_HFDSC,
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.rom_init_timeout = 300,
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.ssp_count = MTL_SSP_COUNT,
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.d0i3_offset = MTL_HDA_VS_D0I3C,
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.read_sdw_lcount = hda_sdw_check_lcount_ext,
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.check_sdw_irq = lnl_dsp_check_sdw_irq,
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.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
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.sdw_process_wakeen = hda_sdw_process_wakeen_common,
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.check_ipc_irq = mtl_dsp_check_ipc_irq,
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.cl_init = mtl_dsp_cl_init,
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.power_down_dsp = mtl_power_down_dsp,
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.disable_interrupts = lnl_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_ACE_4_0,
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.platform = "nvl",
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};
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MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_MTL");
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MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_LNL");
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MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_PTL");
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