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Document the device tree binding for the Tegra238 memory controller. Tegra238 has 8 memory controller channels plus broadcast and stream-id registers. Add the stream ID header (nvidia,tegra238-mc.h) defining ISO and NISO stream IDs for SMMU configuration. Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260427073419.567360-2-amhetre@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA238_MC_H
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/* special clients */
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#define TEGRA238_SID_INVALID 0x0
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#define TEGRA238_SID_PASSTHROUGH 0x7f
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/* ISO stream IDs */
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#define TEGRA238_SID_ISO_NVDISPLAY 0x1
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#define TEGRA238_SID_ISO_APE0 0x2
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#define TEGRA238_SID_ISO_APE1 0x3
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/* NISO stream IDs */
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#define TEGRA238_SID_AON 0x1
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#define TEGRA238_SID_BPMP 0x2
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#define TEGRA238_SID_ETR 0x3
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#define TEGRA238_SID_FDE 0x4
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#define TEGRA238_SID_HC 0x5
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#define TEGRA238_SID_HDA 0x6
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#define TEGRA238_SID_NVDEC 0x7
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#define TEGRA238_SID_NVDISPLAY 0x8
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#define TEGRA238_SID_NVENC 0x9
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#define TEGRA238_SID_OFA 0xa
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#define TEGRA238_SID_PCIE0 0xb
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#define TEGRA238_SID_PCIE1 0xc
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#define TEGRA238_SID_PCIE2 0xd
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#define TEGRA238_SID_PCIE3 0xe
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#define TEGRA238_SID_HWMP_PMA 0xf
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#define TEGRA238_SID_PSC 0x10
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#define TEGRA238_SID_SDMMC1A 0x11
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#define TEGRA238_SID_SDMMC4A 0x12
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#define TEGRA238_SID_SES_SE0 0x13
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#define TEGRA238_SID_SES_SE1 0x14
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#define TEGRA238_SID_SES_SE2 0x15
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#define TEGRA238_SID_SEU1_SE0 0x16
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#define TEGRA238_SID_SEU1_SE1 0x17
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#define TEGRA238_SID_SEU1_SE2 0x18
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#define TEGRA238_SID_TSEC 0x19
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#define TEGRA238_SID_UFSHC 0x1a
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#define TEGRA238_SID_VIC 0x1b
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#define TEGRA238_SID_XUSB_HOST 0x1c
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#define TEGRA238_SID_XUSB_DEV 0x1d
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#define TEGRA238_SID_GPCDMA_0 0x1e
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#define TEGRA238_SID_SMMU_TEST 0x1f
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/* Host1x virtualization clients. */
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#define TEGRA238_SID_HOST1X_CTX0 0x20
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#define TEGRA238_SID_HOST1X_CTX1 0x21
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#define TEGRA238_SID_HOST1X_CTX2 0x22
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#define TEGRA238_SID_HOST1X_CTX3 0x23
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#define TEGRA238_SID_HOST1X_CTX4 0x24
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#define TEGRA238_SID_HOST1X_CTX5 0x25
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#define TEGRA238_SID_HOST1X_CTX6 0x26
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#define TEGRA238_SID_HOST1X_CTX7 0x27
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#define TEGRA238_SID_XUSB_VF0 0x28
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#define TEGRA238_SID_XUSB_VF1 0x29
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#define TEGRA238_SID_XUSB_VF2 0x2a
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#define TEGRA238_SID_XUSB_VF3 0x2b
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/* Host1x command buffers */
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#define TEGRA238_SID_HC_VM0 0x2c
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#define TEGRA238_SID_HC_VM1 0x2d
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#define TEGRA238_SID_HC_VM2 0x2e
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#define TEGRA238_SID_HC_VM3 0x2f
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#define TEGRA238_SID_HC_VM4 0x30
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#define TEGRA238_SID_HC_VM5 0x31
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#define TEGRA238_SID_HC_VM6 0x32
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#define TEGRA238_SID_HC_VM7 0x33
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#endif
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