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0f90f883b3
Document the RPM Network-On-Chip Interconnect for the Qualcomm Shikra platform. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Link: https://patch.msgid.link/20260505-shikra_icc-v3-1-8e03ff27c007@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
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#define MASTER_QUP_CORE_0 0
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#define SLAVE_QUP_CORE_0 1
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#define SNOC_CNOC_MAS 0
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#define MASTER_QDSS_DAP 1
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#define SLAVE_AHB2PHY_USB 2
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#define SLAVE_APSS_THROTTLE_CFG 3
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#define SLAVE_AUDIO 4
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#define SLAVE_BOOT_ROM 5
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#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
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#define SLAVE_CAMERA_CFG 7
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#define SLAVE_CDSP_THROTTLE_CFG 8
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#define SLAVE_CLK_CTL 9
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#define SLAVE_DSP_CFG 10
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#define SLAVE_RBCPR_CX_CFG 11
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#define SLAVE_RBCPR_MX_CFG 12
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#define SLAVE_CRYPTO_0_CFG 13
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#define SLAVE_DDR_SS_CFG 14
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#define SLAVE_DISPLAY_CFG 15
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#define SLAVE_EMAC0_CFG 16
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#define SLAVE_EMAC1_CFG 17
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#define SLAVE_GPU_CFG 18
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#define SLAVE_GPU_THROTTLE_CFG 19
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#define SLAVE_HWKM 20
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#define SLAVE_IMEM_CFG 21
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#define SLAVE_MAPSS 22
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#define SLAVE_MDSP_MPU_CFG 23
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#define SLAVE_MESSAGE_RAM 24
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#define SLAVE_MSS 25
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#define SLAVE_PCIE_CFG 26
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#define SLAVE_PDM 27
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#define SLAVE_PIMEM_CFG 28
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#define SLAVE_PKA_WRAPPER_CFG 29
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#define SLAVE_PMIC_ARB 30
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#define SLAVE_QDSS_CFG 31
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#define SLAVE_QM_CFG 32
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#define SLAVE_QM_MPU_CFG 33
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#define SLAVE_QPIC 34
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#define SLAVE_QUP_0 35
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#define SLAVE_RPM 36
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#define SLAVE_SDCC_1 37
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#define SLAVE_SDCC_2 38
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#define SLAVE_SECURITY 39
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#define SLAVE_SNOC_CFG 40
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#define SNOC_SF_THROTTLE_CFG 41
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#define SLAVE_TLMM 42
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#define SLAVE_TSCSS 43
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#define SLAVE_USB2 44
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#define SLAVE_USB3 45
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#define SLAVE_VENUS_CFG 46
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#define SLAVE_VENUS_THROTTLE_CFG 47
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#define SLAVE_VSENSE_CTRL_CFG 48
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#define SLAVE_SERVICE_CNOC 49
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#define MASTER_LLCC 0
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#define SLAVE_EBI_CH0 1
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#define MASTER_GRAPHICS_3D 0
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#define MASTER_MNOC_HF_MEM_NOC 1
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#define MASTER_ANOC_PCIE_MEM_NOC 2
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#define MASTER_SNOC_SF_MEM_NOC 3
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#define MASTER_AMPSS_M0 4
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#define MASTER_SYS_TCU 5
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#define SLAVE_LLCC 6
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#define SLAVE_MEMNOC_SNOC 7
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#define SLAVE_MEM_NOC_PCIE_SNOC 8
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#define MASTER_CAMNOC_SF 0
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#define MASTER_VIDEO_P0 1
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#define MASTER_VIDEO_PROC 2
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#define SLAVE_MMNRT_VIRT 3
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#define MASTER_CAMNOC_HF 0
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#define MASTER_MDP_PORT0 1
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#define MASTER_MMRT_VIRT 2
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#define SLAVE_MM_MEMNOC 3
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#define MASTER_SNOC_CFG 0
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#define MASTER_TIC 1
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#define MASTER_ANOC_SNOC 2
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#define MASTER_MEMNOC_PCIE 3
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#define MASTER_MEMNOC_SNOC 4
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#define MASTER_PIMEM 5
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#define MASTER_PCIE2_0 6
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#define MASTER_QDSS_BAM 7
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#define MASTER_QPIC 8
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#define MASTER_QUP_0 9
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#define CNOC_SNOC_MAS 10
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#define MASTER_AUDIO 11
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#define MASTER_EMAC_0 12
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#define MASTER_EMAC_1 13
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#define MASTER_QDSS_ETR 14
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#define MASTER_SDCC_1 15
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#define MASTER_SDCC_2 16
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#define MASTER_USB2_0 17
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#define MASTER_USB3 18
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#define MASTER_CRYPTO_CORE0 19
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#define SLAVE_APPSS 20
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#define SLAVE_MCUSS 21
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#define SLAVE_WCSS 22
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#define SLAVE_MEMNOC_SF 23
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#define SNOC_CNOC_SLV 24
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#define SLAVE_BOOTIMEM 25
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#define SLAVE_OCIMEM 26
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#define SLAVE_PIMEM 27
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#define SLAVE_SERVICE_SNOC 28
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#define SLAVE_PCIE2_0 29
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#define SLAVE_QDSS_STM 30
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#define SLAVE_TCU 31
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#define SLAVE_PCIE_MEMNOC 32
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#define SLAVE_ANOC_SNOC 33
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#endif
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