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77ae37018a
In the implementation and integration of the SoC, the DW DisplayPort hardware block can be configured to work in single, dual, quad pixel mode on differnt platforms, so make the pixel mode set by plat_data to support the upcoming rk3576 variant. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20260206010421.443605-3-andyshrk@163.com
28 lines
495 B
C
28 lines
495 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __DW_DP__
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#define __DW_DP__
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#include <linux/device.h>
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struct drm_encoder;
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struct dw_dp;
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enum {
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DW_DP_MP_SINGLE_PIXEL,
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DW_DP_MP_DUAL_PIXEL,
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DW_DP_MP_QUAD_PIXEL,
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};
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struct dw_dp_plat_data {
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u32 max_link_rate;
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u8 pixel_mode;
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};
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struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
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const struct dw_dp_plat_data *plat_data);
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#endif /* __DW_DP__ */
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