mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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99224c151c
With LLVM prior to 17.0.0:
drivers/pinctrl/pinctrl-mpfs-iomux0.c:89:2: error: initializer element is not a compile-time constant
MPFS_IOMUX0_GROUP(spi0),
^~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-mpfs-iomux0.c:79:10: note: expanded from macro 'MPFS_IOMUX0_GROUP'
.mask = BIT(mpfs_iomux0_##_name##_pins[0]), \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/vdso/bits.h:7:19: note: expanded from macro 'BIT'
\#define BIT(nr) (UL(1) << (nr))
^~~~~~~~~~~~~~~
This is a constant, but LLVM prior to a change from Nick to match the
gcc behaviour did not allow this. The macro isn't really all that much
of an idiot-proofing, just change it to the same sort that's in the
gpio2 driver, where a second argument provides the mask/setting.
Reported-by: Nathan Chancellor <nathan@kernel.org>
Link: https://github.com/ClangBuiltLinux/linux/issues/2140
Fixes: 46397274da ("pinctrl: add polarfire soc iomux0 pinmux driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
279 lines
8.6 KiB
C
279 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/bitfield.h>
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#include <linux/cleanup.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/seq_file.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include "core.h"
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#include "pinctrl-utils.h"
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#include "pinconf.h"
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#include "pinmux.h"
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#define MPFS_IOMUX0_REG 0x200
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struct mpfs_iomux0_pinctrl {
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struct pinctrl_dev *pctrl;
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struct device *dev;
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struct regmap *regmap;
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struct pinctrl_desc desc;
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};
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struct mpfs_iomux0_pin_group {
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const char *name;
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const unsigned int *pins;
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u32 mask;
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u32 setting;
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};
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struct mpfs_iomux0_function {
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const char *name;
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const char * const *groups;
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};
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static const struct pinctrl_pin_desc mpfs_iomux0_pins[] = {
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PINCTRL_PIN(0, "spi0"),
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PINCTRL_PIN(1, "spi1"),
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PINCTRL_PIN(2, "i2c0"),
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PINCTRL_PIN(3, "i2c1"),
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PINCTRL_PIN(4, "can0"),
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PINCTRL_PIN(5, "can1"),
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PINCTRL_PIN(6, "qspi"),
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PINCTRL_PIN(7, "uart0"),
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PINCTRL_PIN(8, "uart1"),
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PINCTRL_PIN(9, "uart2"),
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PINCTRL_PIN(10, "uart3"),
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PINCTRL_PIN(11, "uart4"),
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PINCTRL_PIN(12, "mdio0"),
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PINCTRL_PIN(13, "mdio1"),
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};
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static const unsigned int mpfs_iomux0_spi0_pins[] = { 0 };
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static const unsigned int mpfs_iomux0_spi1_pins[] = { 1 };
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static const unsigned int mpfs_iomux0_i2c0_pins[] = { 2 };
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static const unsigned int mpfs_iomux0_i2c1_pins[] = { 3 };
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static const unsigned int mpfs_iomux0_can0_pins[] = { 4 };
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static const unsigned int mpfs_iomux0_can1_pins[] = { 5 };
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static const unsigned int mpfs_iomux0_qspi_pins[] = { 6 };
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static const unsigned int mpfs_iomux0_uart0_pins[] = { 7 };
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static const unsigned int mpfs_iomux0_uart1_pins[] = { 8 };
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static const unsigned int mpfs_iomux0_uart2_pins[] = { 9 };
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static const unsigned int mpfs_iomux0_uart3_pins[] = { 10 };
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static const unsigned int mpfs_iomux0_uart4_pins[] = { 11 };
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static const unsigned int mpfs_iomux0_mdio0_pins[] = { 12 };
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static const unsigned int mpfs_iomux0_mdio1_pins[] = { 13 };
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#define MPFS_IOMUX0_GROUP(_name, _mask) { \
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.name = #_name "_mssio", \
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.pins = mpfs_iomux0_##_name##_pins, \
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.mask = _mask, \
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.setting = 0x0, \
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}, { \
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.name = #_name "_fabric", \
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.pins = mpfs_iomux0_##_name##_pins, \
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.mask = _mask, \
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.setting = _mask, \
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}
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static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] = {
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MPFS_IOMUX0_GROUP(spi0, BIT(0)),
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MPFS_IOMUX0_GROUP(spi1, BIT(1)),
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MPFS_IOMUX0_GROUP(i2c0, BIT(2)),
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MPFS_IOMUX0_GROUP(i2c1, BIT(3)),
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MPFS_IOMUX0_GROUP(can0, BIT(4)),
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MPFS_IOMUX0_GROUP(can1, BIT(5)),
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MPFS_IOMUX0_GROUP(qspi, BIT(6)),
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MPFS_IOMUX0_GROUP(uart0, BIT(7)),
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MPFS_IOMUX0_GROUP(uart1, BIT(8)),
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MPFS_IOMUX0_GROUP(uart2, BIT(9)),
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MPFS_IOMUX0_GROUP(uart3, BIT(10)),
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MPFS_IOMUX0_GROUP(uart4, BIT(11)),
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MPFS_IOMUX0_GROUP(mdio0, BIT(12)),
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MPFS_IOMUX0_GROUP(mdio1, BIT(13)),
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};
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static const char * const mpfs_iomux0_spi0_groups[] = { "spi0_mssio", "spi0_fabric" };
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static const char * const mpfs_iomux0_spi1_groups[] = { "spi1_mssio", "spi1_fabric" };
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static const char * const mpfs_iomux0_i2c0_groups[] = { "i2c0_mssio", "i2c0_fabric" };
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static const char * const mpfs_iomux0_i2c1_groups[] = { "i2c1_mssio", "i2c1_fabric" };
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static const char * const mpfs_iomux0_can0_groups[] = { "can0_mssio", "can0_fabric" };
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static const char * const mpfs_iomux0_can1_groups[] = { "can1_mssio", "can1_fabric" };
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static const char * const mpfs_iomux0_qspi_groups[] = { "qspi_mssio", "qspi_fabric" };
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static const char * const mpfs_iomux0_uart0_groups[] = { "uart0_mssio", "uart0_fabric" };
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static const char * const mpfs_iomux0_uart1_groups[] = { "uart1_mssio", "uart1_fabric" };
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static const char * const mpfs_iomux0_uart2_groups[] = { "uart2_mssio", "uart2_fabric" };
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static const char * const mpfs_iomux0_uart3_groups[] = { "uart3_mssio", "uart3_fabric" };
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static const char * const mpfs_iomux0_uart4_groups[] = { "uart4_mssio", "uart4_fabric" };
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static const char * const mpfs_iomux0_mdio0_groups[] = { "mdio0_mssio", "mdio0_fabric" };
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static const char * const mpfs_iomux0_mdio1_groups[] = { "mdio1_mssio", "mdio1_fabric" };
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#define MPFS_IOMUX0_FUNCTION(_name) { \
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.name = #_name, \
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.groups = mpfs_iomux0_##_name##_groups, \
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}
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static const struct mpfs_iomux0_function mpfs_iomux0_functions[] = {
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MPFS_IOMUX0_FUNCTION(spi0),
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MPFS_IOMUX0_FUNCTION(spi1),
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MPFS_IOMUX0_FUNCTION(i2c0),
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MPFS_IOMUX0_FUNCTION(i2c1),
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MPFS_IOMUX0_FUNCTION(can0),
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MPFS_IOMUX0_FUNCTION(can1),
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MPFS_IOMUX0_FUNCTION(qspi),
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MPFS_IOMUX0_FUNCTION(uart0),
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MPFS_IOMUX0_FUNCTION(uart1),
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MPFS_IOMUX0_FUNCTION(uart2),
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MPFS_IOMUX0_FUNCTION(uart3),
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MPFS_IOMUX0_FUNCTION(uart4),
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MPFS_IOMUX0_FUNCTION(mdio0),
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MPFS_IOMUX0_FUNCTION(mdio1),
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};
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static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
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unsigned int pin)
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{
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struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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u32 val;
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seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin);
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regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val);
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val = (val & BIT(pin)) >> pin;
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seq_printf(seq, "val: %x\n", val);
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}
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static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(mpfs_iomux0_pin_groups);
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}
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static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
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{
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return mpfs_iomux0_pin_groups[selector].name;
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}
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static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
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const unsigned int **pins, unsigned int *num_pins)
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{
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*pins = mpfs_iomux0_pin_groups[selector].pins;
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*num_pins = 1;
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return 0;
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}
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static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops = {
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.get_groups_count = mpfs_iomux0_groups_count,
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.get_group_name = mpfs_iomux0_group_name,
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.get_group_pins = mpfs_iomux0_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinctrl_utils_free_map,
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.pin_dbg_show = mpfs_iomux0_pin_dbg_show,
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};
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static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
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unsigned int gsel)
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{
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struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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struct device *dev = pctrl->dev;
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const struct mpfs_iomux0_pin_group *group;
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const struct mpfs_iomux0_function *function;
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group = &mpfs_iomux0_pin_groups[gsel];
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function = &mpfs_iomux0_functions[fsel];
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dev_dbg(dev, "Setting func %s mask %x setting %x\n",
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function->name, group->mask, group->setting);
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regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->setting);
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return 0;
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}
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static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(mpfs_iomux0_functions);
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}
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static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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return mpfs_iomux0_functions[selector].name;
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}
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static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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*groups = mpfs_iomux0_functions[selector].groups;
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*num_groups = 2;
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return 0;
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}
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static const struct pinmux_ops mpfs_iomux0_pinmux_ops = {
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.get_functions_count = mpfs_iomux0_pinmux_get_funcs_count,
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.get_function_name = mpfs_iomux0_pinmux_get_func_name,
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.get_function_groups = mpfs_iomux0_pinmux_get_groups,
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.set_mux = mpfs_iomux0_pinmux_set_mux,
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};
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static int mpfs_iomux0_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mpfs_iomux0_pinctrl *pctrl;
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pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
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if (!pctrl)
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return -ENOMEM;
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pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
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if (IS_ERR(pctrl->regmap))
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dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
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pctrl->desc.name = dev_name(dev);
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pctrl->desc.pins = mpfs_iomux0_pins;
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pctrl->desc.npins = ARRAY_SIZE(mpfs_iomux0_pins);
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pctrl->desc.pctlops = &mpfs_iomux0_pinctrl_ops;
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pctrl->desc.pmxops = &mpfs_iomux0_pinmux_ops;
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pctrl->desc.owner = THIS_MODULE;
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pctrl->dev = dev;
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platform_set_drvdata(pdev, pctrl);
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pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
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if (IS_ERR(pctrl->pctrl))
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return PTR_ERR(pctrl->pctrl);
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return 0;
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}
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static const struct of_device_id mpfs_iomux0_of_match[] = {
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{ .compatible = "microchip,mpfs-pinctrl-iomux0" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match);
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static struct platform_driver mpfs_iomux0_driver = {
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.driver = {
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.name = "mpfs-pinctrl-iomux0",
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.of_match_table = mpfs_iomux0_of_match,
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},
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.probe = mpfs_iomux0_probe,
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};
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module_platform_driver(mpfs_iomux0_driver);
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MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
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MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver");
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MODULE_LICENSE("GPL");
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