mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-22 02:17:36 -04:00
Introduce a driver for the networking lanes of the 10G Lynx SerDes block, present on the majority of Layerscape and QorIQ (Freescale/NXP) SoCs. As with the 28G Lynx, the SerDes lanes come pre-initialized out of reset and the consumers use them that way outside the Generic PHY framework (for networking, the static configuration remains for the entire SoC lifetime, whereas for SATA and PCIe, the hardware reconfigures itself automatically for other link speeds). The need for the Generic PHY framework comes specifically for networking use cases where a static lane configuration is not sufficient. For example a network MAC is connected to an SFP cage, where various SFP or SFP+ modules can be connected. Each of them may require a different SerDes protocol (SGMII, 1000Base-X, 10GBase-R), which phylink + sfp-bus are responsible of figuring out. The phylink drivers are: - enetc - felix - dpaa_eth (fman_memac) - dpaa2-eth - dpaa2-switch and they all need to reconfigure the SerDes for the requested link mode, using phy_set_mode_ext() (and phy_validate() to see if it is supported in the first place). Note that SerDes 2 on LS1088A is exclusively non-networking, so there is currently no need for this driver. Therefore we skip matching on its compatible string and do not probe on that device. Co-developed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20260610151952.2141019-16-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
78 lines
2.1 KiB
Plaintext
78 lines
2.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
|
|
if (ARCH_MXC && ARM64) || COMPILE_TEST
|
|
|
|
config PHY_FSL_IMX8MQ_USB
|
|
tristate "Freescale i.MX8M USB3 PHY"
|
|
depends on OF && HAS_IOMEM
|
|
depends on TYPEC || TYPEC=n
|
|
select GENERIC_PHY
|
|
default ARCH_MXC && ARM64
|
|
|
|
config PHY_MIXEL_LVDS_PHY
|
|
tristate "Mixel LVDS PHY support"
|
|
depends on OF
|
|
select GENERIC_PHY
|
|
select REGMAP_MMIO
|
|
help
|
|
Enable this to add support for the Mixel LVDS PHY as found
|
|
on NXP's i.MX8qm SoC.
|
|
|
|
config PHY_MIXEL_MIPI_DPHY
|
|
tristate "Mixel MIPI DSI PHY support"
|
|
depends on OF && HAS_IOMEM
|
|
select GENERIC_PHY
|
|
select GENERIC_PHY_MIPI_DPHY
|
|
select REGMAP_MMIO
|
|
help
|
|
Enable this to add support for the Mixel DSI PHY as found
|
|
on NXP's i.MX8 family of SOCs.
|
|
|
|
config PHY_FSL_IMX8M_PCIE
|
|
tristate "Freescale i.MX8M PCIE PHY"
|
|
depends on OF && HAS_IOMEM
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this to add support for the PCIE PHY as found on
|
|
i.MX8M family of SOCs.
|
|
|
|
config PHY_FSL_IMX8QM_HSIO
|
|
tristate "Freescale i.MX8QM HSIO PHY"
|
|
depends on OF && HAS_IOMEM
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this to add support for the HSIO PHY as found on
|
|
i.MX8QM family of SOCs.
|
|
|
|
config PHY_FSL_SAMSUNG_HDMI_PHY
|
|
tristate "Samsung HDMI PHY support"
|
|
depends on OF && HAS_IOMEM && COMMON_CLK
|
|
help
|
|
Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
|
|
endif
|
|
|
|
config PHY_FSL_LYNX_CORE
|
|
tristate
|
|
|
|
config PHY_FSL_LYNX_10G
|
|
tristate "Freescale Layerscape Lynx 10G SerDes PHY support"
|
|
depends on OF
|
|
depends on ARCH_LAYERSCAPE || COMPILE_TEST
|
|
select GENERIC_PHY
|
|
select PHY_FSL_LYNX_CORE
|
|
help
|
|
Enable this to add support for the Lynx 10G SerDes PHY as found on
|
|
NXP's Layerscape platform such as LS1088A or LS1028A.
|
|
|
|
config PHY_FSL_LYNX_28G
|
|
tristate "Freescale Layerscape Lynx 28G SerDes PHY support"
|
|
depends on OF
|
|
depends on ARCH_LAYERSCAPE || COMPILE_TEST
|
|
select GENERIC_PHY
|
|
select PHY_FSL_LYNX_CORE
|
|
help
|
|
Enable this to add support for the Lynx SerDes 28G PHY as
|
|
found on NXP's Layerscape platforms such as LX2160A.
|
|
Used to change the protocol running on SerDes lanes at runtime.
|
|
Only useful for a restricted set of Ethernet protocols.
|