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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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7ef502fb35
The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions only as a root complex, with a single-lane (x1) configuration. The controller includes Type 1 configuration registers, as well as IP specific registers (called AXI registers) required for various adjustments. Hardware manual can be downloaded from the address in the "Link" section. The following steps should be followed to access the manual: 1/ Click the "User Manual" button 2/ Click "Confirm"; this will start downloading an archive 3/ Open the downloaded archive 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables 5/ Open the file r01uh1014ej*-rzg3s.pdf Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12 Link: https://patch.msgid.link/20251119143523.977085-3-claudiu.beznea.uj@bp.renesas.com
67 lines
2.8 KiB
Makefile
67 lines
2.8 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_CADENCE) += cadence/
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obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
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obj-$(CONFIG_PCI_IXP4XX) += pci-ixp4xx.o
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obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
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obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
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obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
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obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
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obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
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obj-$(CONFIG_PCIE_RENESAS_RZG3S_HOST) += pcie-rzg3s-host.o
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obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
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obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
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obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
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obj-$(CONFIG_PCIE_XILINX_CPM) += pcie-xilinx-cpm.o
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obj-$(CONFIG_PCIE_XILINX_DMA_PL) += pcie-xilinx-dma-pl.o
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obj-$(CONFIG_PCI_V3_SEMI) += pci-v3-semi.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
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obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
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obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
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obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
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obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
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obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
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obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
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obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
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obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
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obj-$(CONFIG_VMD) += vmd.o
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obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
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obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
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obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
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obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
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obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
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# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
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obj-y += dwc/
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obj-y += mobiveil/
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obj-y += plda/
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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# They contain MCFG quirks to replace the generic ECAM accessors with
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# device-specific ones that are shared with the DT driver.
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# The ACPI driver is generic and should not require driver-specific
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# config options to be enabled, so we always build these drivers on
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# ARM64 and use internal ifdefs to only build the pieces we need
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# depending on whether ACPI, the DT driver, or both are enabled.
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ifdef CONFIG_ACPI
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ifdef CONFIG_PCI_QUIRKS
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obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
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obj-$(CONFIG_ARM64) += pci-thunder-pem.o
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obj-$(CONFIG_ARM64) += pci-xgene.o
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endif
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endif
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