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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-12-27 11:06:41 -05:00
256a21743d
Rename struct i3c_priv_xfer to struct i3c_xfer, since private xfer in the I3C spec refers only to SDR transfers. Ref: i3c spec ver1.2, section 3, Technical Overview. i3c_xfer will be used for both SDR and HDR. Rename enum i3c_hdr_mode to i3c_xfer_mode. Previous definition need match CCC GET_CAP1 bit position. Use 31 as SDR transfer mode. Add i3c_device_do_xfers() with an xfer mode argument, while keeping i3c_device_do_priv_xfers() as a wrapper that calls i3c_device_do_xfers() with I3C_SDR for backward compatibility. Introduce a 'cmd' field in struct i3c_xfer as an anonymous union with 'rnw', since HDR mode uses read/write commands instead of the SDR address bit. Add .i3c_xfers() callback for master controllers. If not implemented, fall back to SDR with .priv_xfers(). The .priv_xfers() API can be removed once all controllers switch to .i3c_xfers(). Add 'mode_mask' bitmask to advertise controller capability. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20251106-i3c_ddr-v11-1-33a6a66ed095@nxp.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*
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* Author: Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#ifndef I3C_INTERNALS_H
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#define I3C_INTERNALS_H
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#include <linux/i3c/master.h>
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#include <linux/io.h>
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void i3c_bus_normaluse_lock(struct i3c_bus *bus);
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void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
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int i3c_dev_setdasa_locked(struct i3c_dev_desc *dev);
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int i3c_dev_do_xfers_locked(struct i3c_dev_desc *dev,
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struct i3c_xfer *xfers,
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int nxfers, enum i3c_xfer_mode mode);
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int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev);
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int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev);
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int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
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const struct i3c_ibi_setup *req);
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void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
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/**
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* i3c_writel_fifo - Write data buffer to 32bit FIFO
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* @addr: FIFO Address to write to
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* @buf: Pointer to the data bytes to write
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* @nbytes: Number of bytes to write
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*/
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static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
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int nbytes)
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{
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writesl(addr, buf, nbytes / 4);
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if (nbytes & 3) {
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u32 tmp = 0;
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memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
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/*
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* writesl() instead of writel() to keep FIFO
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* byteorder on big-endian targets
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*/
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writesl(addr, &tmp, 1);
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}
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}
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/**
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* i3c_readl_fifo - Read data buffer from 32bit FIFO
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* @addr: FIFO Address to read from
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* @buf: Pointer to the buffer to store read bytes
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* @nbytes: Number of bytes to read
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*/
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static inline void i3c_readl_fifo(const void __iomem *addr, void *buf,
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int nbytes)
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{
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readsl(addr, buf, nbytes / 4);
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if (nbytes & 3) {
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u32 tmp;
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/*
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* readsl() instead of readl() to keep FIFO
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* byteorder on big-endian targets
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*/
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readsl(addr, &tmp, 1);
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memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
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}
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}
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#endif /* I3C_INTERNAL_H */
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