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2299d73562
From Xe2 onward (i.e., all platforms officially supported by the Xe
driver), the GAMSTLB_CTRL register is located at offset 0x477C and
represented by the macro "GAMSTLB_CTRL" in code. However the register
formerly resided at offset 0xCF4C on Xe1-era platforms, and we also have
macro XEHP_GAMSTLB_CTRL that represents this old offset in the
unofficial/developer-only Xe1 code. When tuning for the register was
added for Xe3p_LPG, the old Xe1-era macro was accidentally used instead
of the proper macro for Xe2 and beyond, causing the tuning to not be
applied properly. Use the proper definition so that the correct offset
is written to.
Bspec: 59298
Fixes: 377c89bfaa ("drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB")
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260410-xe3p_tuning-v1-2-e206a62ee38f@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 0b1676eafdd1ba5a5436bdca0d2a25ce56699783)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
272 lines
9.0 KiB
C
272 lines
9.0 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_tuning.h"
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#include <kunit/visibility.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "regs/xe_engine_regs.h"
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#include "regs/xe_gt_regs.h"
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#include "xe_gt_types.h"
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#include "xe_platform_types.h"
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#include "xe_rtp.h"
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#include "xe_sriov.h"
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#undef XE_REG_MCR
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#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
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static const struct xe_rtp_entry_sr gt_tunings[] = {
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{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
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XE_RTP_RULES(PLATFORM(DG2)),
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XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
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},
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{ XE_RTP_NAME("Tuning: 32B Access Enable"),
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XE_RTP_RULES(PLATFORM(DG2)),
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XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
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},
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/* Xe2 */
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{ XE_RTP_NAME("Tuning: L3 cache"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
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XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{ XE_RTP_NAME("Tuning: L3 cache - media"),
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XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 3499)),
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XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{ XE_RTP_NAME("Tuning: Compression Overfetch"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
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FUNC(xe_rtp_match_has_flat_ccs)),
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XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
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SET(CCCHKNREG1, L3CMPCTRL))
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},
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{ XE_RTP_NAME("Tuning: Compression Overfetch - media"),
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XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
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SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
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},
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{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
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XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
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},
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{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
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XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
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},
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{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
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FUNC(xe_rtp_match_has_flat_ccs)),
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XE_RTP_ACTIONS(SET(L3SQCREG2,
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COMPMEMRD256BOVRFETCHEN))
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},
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{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
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XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
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FUNC(xe_rtp_match_has_flat_ccs)),
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XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
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COMPMEMRD256BOVRFETCHEN))
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},
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{ XE_RTP_NAME("Tuning: Stateless compression control"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
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REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
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},
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{ XE_RTP_NAME("Tuning: Stateless compression control - media"),
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XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
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REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
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},
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{ XE_RTP_NAME("Tuning: L3 RW flush all Cache"),
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XE_RTP_RULES(GRAPHICS_VERSION(2004)),
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XE_RTP_ACTIONS(SET(SCRATCH3_LBCF, RWFLUSHALLEN))
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},
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{ XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
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XE_RTP_RULES(MEDIA_VERSION(2000)),
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XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
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},
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/* Xe3p */
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{ XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
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IS_INTEGRATED),
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XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
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BANK_HASH_4KB_MODE))
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},
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};
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static const struct xe_rtp_entry_sr engine_tunings[] = {
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{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(CLR(XELP_GARBCNTL, XELP_BUS_HASH_CTL_BIT_EXC))
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},
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{ XE_RTP_NAME("Tuning: Set Indirect State Override"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
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ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))
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},
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{ XE_RTP_NAME("Tuning: Disable NULL query for Anyhit Shader"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
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},
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{ XE_RTP_NAME("Tuning: disable HW reporting of ctx switch to GHWSP"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3500, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
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GHWSP_CSB_REPORT_DIS,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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};
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static const struct xe_rtp_entry_sr lrc_tunings[] = {
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{ XE_RTP_NAME("Tuning: Windower HW Filtering"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, HW_FILTERING))
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},
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/* DG2 */
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{ XE_RTP_NAME("Tuning: L3 cache"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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{ XE_RTP_NAME("Tuning: TDS gang timer"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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/* read verification is ignored as in i915 - need to check enabling */
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XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
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FF_MODE2_TDS_TIMER_MASK,
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FF_MODE2_TDS_TIMER_128))
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},
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{ XE_RTP_NAME("Tuning: TBIMR fast clip"),
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XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
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},
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/* Xe_LPG */
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{ XE_RTP_NAME("Tuning: L3 cache"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
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REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
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},
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/* Xe2_HPG */
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{ XE_RTP_NAME("Tuning: vs hit max value"),
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XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
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REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
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},
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};
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/**
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* xe_tuning_init - initialize gt with tunings bookkeeping
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* @gt: GT instance to initialize
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*
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* Returns 0 for success, negative error code otherwise.
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*/
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int xe_tuning_init(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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size_t n_lrc, n_engine, n_gt, total;
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unsigned long *p;
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n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_tunings));
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n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_tunings));
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n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_tunings));
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total = n_gt + n_engine + n_lrc;
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p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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gt->tuning_active.gt = p;
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p += n_gt;
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gt->tuning_active.engine = p;
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p += n_engine;
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gt->tuning_active.lrc = p;
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return 0;
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}
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ALLOW_ERROR_INJECTION(xe_tuning_init, ERRNO); /* See xe_pci_probe() */
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void xe_tuning_process_gt(struct xe_gt *gt)
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{
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
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xe_rtp_process_ctx_enable_active_tracking(&ctx,
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gt->tuning_active.gt,
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ARRAY_SIZE(gt_tunings));
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xe_rtp_process_to_sr(&ctx, gt_tunings, ARRAY_SIZE(gt_tunings),
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>->reg_sr, false);
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}
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EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
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void xe_tuning_process_engine(struct xe_hw_engine *hwe)
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{
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
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xe_rtp_process_ctx_enable_active_tracking(&ctx,
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hwe->gt->tuning_active.engine,
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ARRAY_SIZE(engine_tunings));
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xe_rtp_process_to_sr(&ctx, engine_tunings, ARRAY_SIZE(engine_tunings),
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&hwe->reg_sr, false);
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}
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EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
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/**
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* xe_tuning_process_lrc - process lrc tunings
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* @hwe: engine instance to process tunings for
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*
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* Process LRC table for this platform, saving in @hwe all the tunings that need
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* to be applied on context restore. These are tunings touching registers that
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* are part of the HW context image.
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*/
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void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
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{
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
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xe_rtp_process_ctx_enable_active_tracking(&ctx,
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hwe->gt->tuning_active.lrc,
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ARRAY_SIZE(lrc_tunings));
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xe_rtp_process_to_sr(&ctx, lrc_tunings, ARRAY_SIZE(lrc_tunings),
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&hwe->reg_lrc, true);
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}
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/**
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* xe_tuning_dump() - Dump GT tuning info into a drm printer.
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* @gt: the &xe_gt
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* @p: the &drm_printer
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*
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* Return: always 0.
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*/
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int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
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{
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size_t idx;
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drm_printf(p, "GT Tunings\n");
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for_each_set_bit(idx, gt->tuning_active.gt, ARRAY_SIZE(gt_tunings))
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drm_printf_indent(p, 1, "%s\n", gt_tunings[idx].name);
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drm_puts(p, "\n");
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drm_printf(p, "Engine Tunings\n");
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for_each_set_bit(idx, gt->tuning_active.engine, ARRAY_SIZE(engine_tunings))
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drm_printf_indent(p, 1, "%s\n", engine_tunings[idx].name);
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drm_puts(p, "\n");
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drm_printf(p, "LRC Tunings\n");
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for_each_set_bit(idx, gt->tuning_active.lrc, ARRAY_SIZE(lrc_tunings))
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drm_printf_indent(p, 1, "%s\n", lrc_tunings[idx].name);
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return 0;
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}
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