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609fc8766d
DMABUF_MOVE_NOTIFY was introduced in 2018 and has been marked as experimental and disabled by default ever since. Six years later, all new importers implement this callback. It is therefore reasonable to drop CONFIG_DMABUF_MOVE_NOTIFY and always build DMABUF with support for it enabled. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://lore.kernel.org/r/20260124-dmabuf-revoke-v5-3-f98fca917e96@nvidia.com Signed-off-by: Christian König <christian.koenig@amd.com>
41 lines
1.4 KiB
Plaintext
41 lines
1.4 KiB
Plaintext
# SPDX-License-Identifier: MIT
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#
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# Heterogeneous system architecture configuration
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#
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config HSA_AMD
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bool "HSA kernel driver for AMD GPU devices"
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depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64 || (RISCV && 64BIT) || (LOONGARCH && 64BIT))
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select HMM_MIRROR
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select MMU_NOTIFIER
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select DRM_AMDGPU_USERPTR
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help
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Enable this if you want to use HSA features on AMD GPU devices.
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config HSA_AMD_SVM
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bool "Enable HMM-based shared virtual memory manager"
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depends on HSA_AMD && DEVICE_PRIVATE
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default y
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select HMM_MIRROR
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select MMU_NOTIFIER
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help
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Enable this to use unified memory and managed memory in HIP. This
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memory manager supports two modes of operation. One based on
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preemptions and one based on page faults. To enable page fault
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based memory management on most GFXv9 GPUs, set the module
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parameter amdgpu.noretry=0.
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config HSA_AMD_P2P
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bool "HSA kernel driver support for peer-to-peer for AMD GPU devices"
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depends on HSA_AMD && PCI_P2PDMA
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help
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Enable peer-to-peer (P2P) communication between AMD GPUs over
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the PCIe bus. This can improve performance of multi-GPU compute
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applications and libraries by enabling GPUs to access data directly
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in peer GPUs' memory without intermediate copies in system memory.
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This P2P feature is only enabled on compatible chipsets, and between
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GPUs with large memory BARs that expose the entire VRAM in PCIe bus
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address space within the physical address limits of the GPUs.
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