mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-12-27 10:01:39 -05:00
dae9750105
The manuals of 2K2000 says both BIT_CTRL_MODE and BYTE_CTRL_MODE are
supported but the latter is recommended. Also on 2K3000, per the ACPI
DSDT the GPIO controller is compatible with 2K2000, but it fails to
operate GPIOs 62 and 63 (and maybe others) using BIT_CTRL_MODE.
Using BYTE_CTRL_MODE also makes those 2K3000 GPIOs work.
Fixes: 3feb70a617 ("gpio: loongson: add more gpio chip support")
Cc: stable@vger.kernel.org
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://lore.kernel.org/r/20251128075033.255821-1-xry111@xry111.site
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
580 lines
15 KiB
C
580 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Loongson GPIO Support
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*
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include <linux/reset.h>
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#include <asm/types.h>
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enum loongson_gpio_mode {
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BIT_CTRL_MODE,
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BYTE_CTRL_MODE,
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};
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struct loongson_gpio_chip_data {
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const char *label;
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enum loongson_gpio_mode mode;
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unsigned int conf_offset;
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unsigned int out_offset;
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unsigned int in_offset;
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unsigned int inten_offset;
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unsigned int intpol_offset;
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unsigned int intedge_offset;
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unsigned int intclr_offset;
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unsigned int intsts_offset;
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unsigned int intdual_offset;
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unsigned int intr_num;
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irq_flow_handler_t irq_handler;
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const struct irq_chip *girqchip;
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};
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struct loongson_gpio_chip {
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struct gpio_generic_chip chip;
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spinlock_t lock;
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void __iomem *reg_base;
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const struct loongson_gpio_chip_data *chip_data;
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};
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static inline struct loongson_gpio_chip *to_loongson_gpio_chip(struct gpio_chip *chip)
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{
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return container_of(to_gpio_generic_chip(chip),
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struct loongson_gpio_chip, chip);
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}
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static inline void loongson_commit_direction(struct loongson_gpio_chip *lgpio, unsigned int pin,
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int input)
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{
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u8 bval = input ? 1 : 0;
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writeb(bval, lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
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}
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static void loongson_commit_level(struct loongson_gpio_chip *lgpio, unsigned int pin, int high)
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{
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u8 bval = high ? 1 : 0;
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writeb(bval, lgpio->reg_base + lgpio->chip_data->out_offset + pin);
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}
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static int loongson_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
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{
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unsigned long flags;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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spin_lock_irqsave(&lgpio->lock, flags);
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loongson_commit_direction(lgpio, pin, 1);
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spin_unlock_irqrestore(&lgpio->lock, flags);
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return 0;
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}
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static int loongson_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, int value)
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{
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unsigned long flags;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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spin_lock_irqsave(&lgpio->lock, flags);
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loongson_commit_level(lgpio, pin, value);
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loongson_commit_direction(lgpio, pin, 0);
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spin_unlock_irqrestore(&lgpio->lock, flags);
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return 0;
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}
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static int loongson_gpio_get(struct gpio_chip *chip, unsigned int pin)
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{
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u8 bval;
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int val;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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bval = readb(lgpio->reg_base + lgpio->chip_data->in_offset + pin);
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val = bval & 1;
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return val;
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}
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static int loongson_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
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{
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u8 bval;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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bval = readb(lgpio->reg_base + lgpio->chip_data->conf_offset + pin);
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if (bval & 1)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int loongson_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
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{
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unsigned long flags;
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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spin_lock_irqsave(&lgpio->lock, flags);
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loongson_commit_level(lgpio, pin, value);
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spin_unlock_irqrestore(&lgpio->lock, flags);
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return 0;
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}
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static int loongson_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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unsigned int u;
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struct platform_device *pdev = to_platform_device(chip->parent);
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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if (lgpio->chip_data->mode == BIT_CTRL_MODE) {
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/* Get the register index from offset then multiply by bytes per register */
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u = readl(lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4);
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u |= BIT(offset % 32);
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writel(u, lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4);
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} else {
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writeb(1, lgpio->reg_base + lgpio->chip_data->inten_offset + offset);
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}
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return platform_get_irq(pdev, offset);
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}
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static void loongson_gpio_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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irq_hw_number_t hwirq = irqd_to_hwirq(data);
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writeb(0x1, lgpio->reg_base + lgpio->chip_data->intclr_offset + hwirq);
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}
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static void loongson_gpio_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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irq_hw_number_t hwirq = irqd_to_hwirq(data);
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writeb(0x0, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq);
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}
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static void loongson_gpio_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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irq_hw_number_t hwirq = irqd_to_hwirq(data);
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writeb(0x1, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq);
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}
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static int loongson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
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irq_hw_number_t hwirq = irqd_to_hwirq(data);
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u8 pol = 0, edge = 0, dual = 0;
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if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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edge = 1;
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dual = 1;
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irq_set_handler_locked(data, handle_edge_irq);
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} else {
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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pol = 1;
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fallthrough;
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(data, handle_level_irq);
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break;
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case IRQ_TYPE_EDGE_RISING:
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pol = 1;
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fallthrough;
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case IRQ_TYPE_EDGE_FALLING:
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edge = 1;
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irq_set_handler_locked(data, handle_edge_irq);
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break;
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default:
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return -EINVAL;
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}
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}
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writeb(pol, lgpio->reg_base + lgpio->chip_data->intpol_offset + hwirq);
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writeb(edge, lgpio->reg_base + lgpio->chip_data->intedge_offset + hwirq);
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writeb(dual, lgpio->reg_base + lgpio->chip_data->intdual_offset + hwirq);
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return 0;
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}
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static void loongson_gpio_ls2k0300_irq_handler(struct irq_desc *desc)
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{
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struct loongson_gpio_chip *lgpio = irq_desc_get_handler_data(desc);
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struct irq_chip *girqchip = irq_desc_get_chip(desc);
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int i;
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chained_irq_enter(girqchip, desc);
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for (i = 0; i < lgpio->chip.gc.ngpio; i++) {
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/*
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* For the GPIO controller of LS2K0300, interrupts status bits
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* may be wrongly set even if the corresponding interrupt is
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* disabled. Thus interrupt enable bits are checked along with
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* status bits to detect interrupts reliably.
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*/
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if (readb(lgpio->reg_base + lgpio->chip_data->intsts_offset + i) &&
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readb(lgpio->reg_base + lgpio->chip_data->inten_offset + i))
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generic_handle_domain_irq(lgpio->chip.gc.irq.domain, i);
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}
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chained_irq_exit(girqchip, desc);
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}
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static const struct irq_chip loongson_gpio_ls2k0300_irqchip = {
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.irq_ack = loongson_gpio_irq_ack,
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.irq_mask = loongson_gpio_irq_mask,
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.irq_unmask = loongson_gpio_irq_unmask,
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.irq_set_type = loongson_gpio_irq_set_type,
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.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int loongson_gpio_init_irqchip(struct platform_device *pdev,
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struct loongson_gpio_chip *lgpio)
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{
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const struct loongson_gpio_chip_data *data = lgpio->chip_data;
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struct gpio_chip *chip = &lgpio->chip.gc;
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int i;
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chip->irq.default_type = IRQ_TYPE_NONE;
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chip->irq.handler = handle_bad_irq;
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chip->irq.parent_handler = data->irq_handler;
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chip->irq.parent_handler_data = lgpio;
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gpio_irq_chip_set_chip(&chip->irq, data->girqchip);
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chip->irq.num_parents = data->intr_num;
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chip->irq.parents = devm_kcalloc(&pdev->dev, data->intr_num,
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sizeof(*chip->irq.parents), GFP_KERNEL);
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if (!chip->parent)
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return -ENOMEM;
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for (i = 0; i < data->intr_num; i++) {
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int ret;
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ret = platform_get_irq(pdev, i);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret,
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"failed to get IRQ %d\n", i);
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chip->irq.parents[i] = ret;
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}
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for (i = 0; i < data->intr_num; i++) {
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writeb(0x0, lgpio->reg_base + data->inten_offset + i);
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writeb(0x1, lgpio->reg_base + data->intclr_offset + i);
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}
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return 0;
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}
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static int loongson_gpio_init(struct platform_device *pdev, struct loongson_gpio_chip *lgpio,
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void __iomem *reg_base)
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{
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struct gpio_generic_chip_config config;
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int ret;
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lgpio->reg_base = reg_base;
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if (lgpio->chip_data->mode == BIT_CTRL_MODE) {
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config = (struct gpio_generic_chip_config) {
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.dev = &pdev->dev,
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.sz = 8,
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.dat = lgpio->reg_base + lgpio->chip_data->in_offset,
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.set = lgpio->reg_base + lgpio->chip_data->out_offset,
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.dirin = lgpio->reg_base + lgpio->chip_data->conf_offset,
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};
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ret = gpio_generic_chip_init(&lgpio->chip, &config);
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if (ret) {
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dev_err(&pdev->dev, "unable to init generic GPIO\n");
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return ret;
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}
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} else {
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lgpio->chip.gc.direction_input = loongson_gpio_direction_input;
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lgpio->chip.gc.get = loongson_gpio_get;
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lgpio->chip.gc.get_direction = loongson_gpio_get_direction;
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lgpio->chip.gc.direction_output = loongson_gpio_direction_output;
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lgpio->chip.gc.set = loongson_gpio_set;
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lgpio->chip.gc.parent = &pdev->dev;
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lgpio->chip.gc.base = -1;
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spin_lock_init(&lgpio->lock);
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}
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lgpio->chip.gc.label = lgpio->chip_data->label;
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lgpio->chip.gc.can_sleep = false;
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if (lgpio->chip_data->girqchip) {
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ret = loongson_gpio_init_irqchip(pdev, lgpio);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "failed to initialize irqchip\n");
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} else if (lgpio->chip_data->inten_offset) {
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lgpio->chip.gc.to_irq = loongson_gpio_to_irq;
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}
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return devm_gpiochip_add_data(&pdev->dev, &lgpio->chip.gc, lgpio);
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}
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static int loongson_gpio_probe(struct platform_device *pdev)
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{
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void __iomem *reg_base;
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struct loongson_gpio_chip *lgpio;
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struct device *dev = &pdev->dev;
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struct reset_control *rst;
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lgpio = devm_kzalloc(dev, sizeof(*lgpio), GFP_KERNEL);
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if (!lgpio)
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return -ENOMEM;
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lgpio->chip_data = device_get_match_data(dev);
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL);
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if (IS_ERR(rst))
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return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get reset control\n");
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return loongson_gpio_init(pdev, lgpio, reg_base);
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}
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data = {
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.label = "ls2k_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x0,
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.in_offset = 0x20,
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.out_offset = 0x10,
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.inten_offset = 0x30,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k0300_data = {
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.label = "ls2k0300_gpio",
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.mode = BYTE_CTRL_MODE,
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.conf_offset = 0x800,
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.in_offset = 0xa00,
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.out_offset = 0x900,
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.inten_offset = 0xb00,
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.intpol_offset = 0xc00,
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.intedge_offset = 0xd00,
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.intclr_offset = 0xe00,
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.intsts_offset = 0xf00,
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.intdual_offset = 0xf80,
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.intr_num = 7,
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.irq_handler = loongson_gpio_ls2k0300_irq_handler,
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.girqchip = &loongson_gpio_ls2k0300_irqchip,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k0500_data0 = {
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.label = "ls2k0500_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x0,
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.in_offset = 0x8,
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.out_offset = 0x10,
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.inten_offset = 0xb0,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k0500_data1 = {
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.label = "ls2k0500_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x0,
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.in_offset = 0x8,
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.out_offset = 0x10,
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.inten_offset = 0x98,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k2000_data0 = {
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.label = "ls2k2000_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x0,
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.in_offset = 0xc,
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.out_offset = 0x8,
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.inten_offset = 0x14,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k2000_data1 = {
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.label = "ls2k2000_gpio",
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.mode = BYTE_CTRL_MODE,
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.conf_offset = 0x800,
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.in_offset = 0xa00,
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.out_offset = 0x900,
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.inten_offset = 0xb00,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls2k2000_data2 = {
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.label = "ls2k2000_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x4,
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.in_offset = 0x8,
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.out_offset = 0x0,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls3a5000_data = {
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.label = "ls3a5000_gpio",
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.mode = BIT_CTRL_MODE,
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.conf_offset = 0x0,
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.in_offset = 0xc,
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.out_offset = 0x8,
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.inten_offset = 0x14,
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};
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static const struct loongson_gpio_chip_data loongson_gpio_ls7a_data = {
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.label = "ls7a_gpio",
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.mode = BYTE_CTRL_MODE,
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.conf_offset = 0x800,
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.in_offset = 0xa00,
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.out_offset = 0x900,
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.inten_offset = 0xb00,
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};
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/* LS7A2000 chipset GPIO */
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static const struct loongson_gpio_chip_data loongson_gpio_ls7a2000_data0 = {
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.label = "ls7a2000_gpio",
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.mode = BYTE_CTRL_MODE,
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.conf_offset = 0x800,
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.in_offset = 0xa00,
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.out_offset = 0x900,
|
|
.inten_offset = 0xb00,
|
|
};
|
|
|
|
/* LS7A2000 ACPI GPIO */
|
|
static const struct loongson_gpio_chip_data loongson_gpio_ls7a2000_data1 = {
|
|
.label = "ls7a2000_gpio",
|
|
.mode = BIT_CTRL_MODE,
|
|
.conf_offset = 0x4,
|
|
.in_offset = 0x8,
|
|
.out_offset = 0x0,
|
|
};
|
|
|
|
/* Loongson-3A6000 node GPIO */
|
|
static const struct loongson_gpio_chip_data loongson_gpio_ls3a6000_data = {
|
|
.label = "ls3a6000_gpio",
|
|
.mode = BIT_CTRL_MODE,
|
|
.conf_offset = 0x0,
|
|
.in_offset = 0xc,
|
|
.out_offset = 0x8,
|
|
.inten_offset = 0x14,
|
|
};
|
|
|
|
static const struct of_device_id loongson_gpio_of_match[] = {
|
|
{
|
|
.compatible = "loongson,ls2k-gpio",
|
|
.data = &loongson_gpio_ls2k_data,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls2k0300-gpio",
|
|
.data = &loongson_gpio_ls2k0300_data,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls2k0500-gpio0",
|
|
.data = &loongson_gpio_ls2k0500_data0,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls2k0500-gpio1",
|
|
.data = &loongson_gpio_ls2k0500_data1,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls2k2000-gpio0",
|
|
.data = &loongson_gpio_ls2k2000_data0,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls2k2000-gpio1",
|
|
.data = &loongson_gpio_ls2k2000_data1,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls2k2000-gpio2",
|
|
.data = &loongson_gpio_ls2k2000_data2,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls3a5000-gpio",
|
|
.data = &loongson_gpio_ls3a5000_data,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls7a-gpio",
|
|
.data = &loongson_gpio_ls7a_data,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls7a2000-gpio1",
|
|
.data = &loongson_gpio_ls7a2000_data0,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls7a2000-gpio2",
|
|
.data = &loongson_gpio_ls7a2000_data1,
|
|
},
|
|
{
|
|
.compatible = "loongson,ls3a6000-gpio",
|
|
.data = &loongson_gpio_ls3a6000_data,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, loongson_gpio_of_match);
|
|
|
|
static const struct acpi_device_id loongson_gpio_acpi_match[] = {
|
|
{
|
|
.id = "LOON0002",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls7a_data,
|
|
},
|
|
{
|
|
.id = "LOON0007",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls3a5000_data,
|
|
},
|
|
{
|
|
.id = "LOON000A",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls2k2000_data0,
|
|
},
|
|
{
|
|
.id = "LOON000B",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls2k2000_data1,
|
|
},
|
|
{
|
|
.id = "LOON000C",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls2k2000_data2,
|
|
},
|
|
{
|
|
.id = "LOON000D",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls7a2000_data0,
|
|
},
|
|
{
|
|
.id = "LOON000E",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls7a2000_data1,
|
|
},
|
|
{
|
|
.id = "LOON000F",
|
|
.driver_data = (kernel_ulong_t)&loongson_gpio_ls3a6000_data,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, loongson_gpio_acpi_match);
|
|
|
|
static struct platform_driver loongson_gpio_driver = {
|
|
.driver = {
|
|
.name = "loongson-gpio",
|
|
.of_match_table = loongson_gpio_of_match,
|
|
.acpi_match_table = loongson_gpio_acpi_match,
|
|
},
|
|
.probe = loongson_gpio_probe,
|
|
};
|
|
|
|
static int __init loongson_gpio_setup(void)
|
|
{
|
|
return platform_driver_register(&loongson_gpio_driver);
|
|
}
|
|
postcore_initcall(loongson_gpio_setup);
|
|
|
|
MODULE_DESCRIPTION("Loongson gpio driver");
|
|
MODULE_LICENSE("GPL");
|