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525ad89dd9
The NPU cores have their own access to the memory bus, and this isn't cache coherent with the CPUs. Add IOCTLs so userspace can mark when the caches need to be flushed, and also when a writer job needs to be waited for before the buffer can be accessed from the CPU. Initially based on the same IOCTLs from the Etnaviv driver. v2: - Don't break UABI by reordering the IOCTL IDs (Jeff Hugo) v3: - Check that padding fields in IOCTLs are zero (Jeff Hugo) v6: - Fix conversion logic to make sure we use DMA_BIDIRECTIONAL when needed (Lucas Stach) v8: - Always sync BOs in both directions (Robin Murphy) Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-5-77ebd484941e@tomeuvizoso.net
35 lines
915 B
C
35 lines
915 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
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#ifndef __ROCKET_GEM_H__
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#define __ROCKET_GEM_H__
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#include <drm/drm_gem_shmem_helper.h>
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struct rocket_gem_object {
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struct drm_gem_shmem_object base;
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struct rocket_file_priv *driver_priv;
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struct rocket_iommu_domain *domain;
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struct drm_mm_node mm;
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size_t size;
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u32 offset;
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};
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struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size);
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int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file);
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int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file);
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int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file);
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static inline
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struct rocket_gem_object *to_rocket_bo(struct drm_gem_object *obj)
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{
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return container_of(to_drm_gem_shmem_obj(obj), struct rocket_gem_object, base);
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}
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#endif
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