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c006978163
NPU firmware requires a host-allocated work buffer for hardware contexts. Allocate a 4 MB host buffer and attach it to device during device init. Refactor aie2_alloc_msg_buffer() and aie2_free_msg_buffer() into common helpers by moving them to aie.c and renaming them to amdxdna_alloc_msg_buffer() and amdxdna_free_msg_buffer(), allowing both AIE2 and AIE4 to reuse the implementation. Signed-off-by: Nishad Saraf <nishads@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/all/20260505160936.3917732-7-lizhi.hou@amd.com/
121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2026, Advanced Micro Devices, Inc.
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*/
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#ifndef _AIE_H_
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#define _AIE_H_
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#include <drm/amdxdna_accel.h>
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#include "amdxdna_pci_drv.h"
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#include "amdxdna_mailbox.h"
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#define AIE_INTERVAL 20000 /* us */
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#define AIE_TIMEOUT 1000000 /* us */
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struct psp_device;
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struct smu_device;
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struct aie_device {
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struct amdxdna_dev *xdna;
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struct mailbox_channel *mgmt_chann;
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struct xdna_mailbox_chann_res mgmt_x2i;
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struct xdna_mailbox_chann_res mgmt_i2x;
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u32 mgmt_chan_idx;
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u32 mgmt_prot_major;
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u32 mgmt_prot_minor;
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unsigned long feature_mask;
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struct psp_device *psp_hdl;
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struct smu_device *smu_hdl;
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struct amdxdna_drm_query_aie_metadata metadata;
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};
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#define DECLARE_AIE_MSG(name, op) \
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DECLARE_XDNA_MSG_COMMON(name, op, -1)
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#define AIE_FEATURE_ON(aie, feature) test_bit(feature, &(aie)->feature_mask)
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#define PSP_REG_BAR(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].bar_idx)
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#define PSP_REG_OFF(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].offset)
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#define SMU_REG_BAR(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].bar_idx)
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#define SMU_REG_OFF(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].offset)
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#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \
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[reg_name] = {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE}
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enum smu_reg_idx {
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SMU_CMD_REG = 0,
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SMU_ARG_REG,
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SMU_INTR_REG,
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SMU_RESP_REG,
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SMU_OUT_REG,
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SMU_MAX_REGS /* Keep this at the end */
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};
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enum psp_reg_idx {
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PSP_CMD_REG = 0,
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PSP_ARG0_REG,
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PSP_ARG1_REG,
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PSP_ARG2_REG,
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PSP_NUM_IN_REGS, /* number of input registers */
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PSP_INTR_REG = PSP_NUM_IN_REGS,
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PSP_STATUS_REG,
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PSP_RESP_REG,
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PSP_PWAITMODE_REG,
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PSP_MAX_REGS /* Keep this at the end */
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};
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struct aie_bar_off_pair {
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int bar_idx;
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u32 offset;
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};
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struct smu_config {
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void __iomem *smu_regs[SMU_MAX_REGS];
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};
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struct psp_config {
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const void *fw_buf;
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u32 fw_size;
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const void *certfw_buf;
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u32 certfw_size;
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void __iomem *psp_regs[PSP_MAX_REGS];
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u32 arg2_mask;
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u32 notify_val;
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};
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/* Device revision to VBNV string mapping table entry */
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struct amdxdna_rev_vbnv {
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u32 revision;
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const char *vbnv;
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};
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/* aie.c */
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void aie_dump_mgmt_chann_debug(struct aie_device *aie);
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void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann);
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int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg);
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int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor);
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void amdxdna_vbnv_init(struct amdxdna_dev *xdna);
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int amdxdna_get_metadata(struct aie_device *aie, struct amdxdna_client *client,
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struct amdxdna_drm_get_info *args);
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void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size,
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dma_addr_t *dma_addr);
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void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size,
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void *cpu_addr, dma_addr_t dma_addr);
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/* aie_psp.c */
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struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf);
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int aie_psp_start(struct psp_device *psp);
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void aie_psp_stop(struct psp_device *psp);
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int aie_psp_waitmode_poll(struct psp_device *psp);
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/* aie_smu.c */
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struct smu_device *aiem_smu_create(struct drm_device *ddev, struct smu_config *conf);
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int aie_smu_init(struct smu_device *smu);
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void aie_smu_fini(struct smu_device *smu);
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int aie_smu_set_clocks(struct smu_device *smu, u32 *npuclk, u32 *hclk);
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int aie_smu_set_dpm(struct smu_device *smu, u32 dpm_level);
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#endif /* _AIE_H_ */
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