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52448a0a73
Different with legacy PEBS, arch-PEBS provides per-counter PEBS data configuration by programing MSR IA32_PMC_GPx/FXx_CFG_C MSRs. This patch obtains PEBS data configuration from event attribute and then writes the PEBS data configuration to MSR IA32_PMC_GPx/FXx_CFG_C and enable corresponding PEBS groups. Please notice this patch only enables XMM SIMD regs sampling for arch-PEBS, the other SIMD regs (OPMASK/YMM/ZMM) sampling on arch-PEBS would be supported after PMI based SIMD regs (OPMASK/YMM/ZMM) sampling is supported. Co-developed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251029102136.61364-12-dapeng1.mi@linux.intel.com
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
#ifndef _ASM_INTEL_DS_H
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#define _ASM_INTEL_DS_H
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#include <linux/percpu-defs.h>
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#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
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#define PEBS_BUFFER_SHIFT 4
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#define PEBS_BUFFER_SIZE (PAGE_SIZE << PEBS_BUFFER_SHIFT)
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/*
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* The largest PEBS record could consume a page, ensure
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* a record at least can be written after triggering PMI.
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*/
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#define ARCH_PEBS_THRESH_MULTI ((PEBS_BUFFER_SIZE - PAGE_SIZE) >> PEBS_BUFFER_SHIFT)
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#define ARCH_PEBS_THRESH_SINGLE 1
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/* The maximal number of PEBS events: */
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#define MAX_PEBS_EVENTS_FMT4 8
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#define MAX_PEBS_EVENTS 32
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#define MAX_PEBS_EVENTS_MASK GENMASK_ULL(MAX_PEBS_EVENTS - 1, 0)
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#define MAX_FIXED_PEBS_EVENTS 16
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/*
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* A debug store configuration.
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*
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* We only support architectures that use 64bit fields.
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*/
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struct debug_store {
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u64 bts_buffer_base;
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u64 bts_index;
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u64 bts_absolute_maximum;
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u64 bts_interrupt_threshold;
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u64 pebs_buffer_base;
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u64 pebs_index;
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u64 pebs_absolute_maximum;
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u64 pebs_interrupt_threshold;
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u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];
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} __aligned(PAGE_SIZE);
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DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
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struct debug_store_buffers {
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char bts_buffer[BTS_BUFFER_SIZE];
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char pebs_buffer[PEBS_BUFFER_SIZE];
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};
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#endif
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