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a96ef5848c
Previously different architectures were using random sources of
differing strength and cost to decide the random kstack offset. A number
of architectures (loongarch, powerpc, s390, x86) were using their
timestamp counter, at whatever the frequency happened to be. Other
arches (arm64, riscv) were using entropy from the crng via
get_random_u16().
There have been concerns that in some cases the timestamp counters may
be too weak, because they can be easily guessed or influenced by user
space. And get_random_u16() has been shown to be too costly for the
level of protection kstack offset randomization provides.
So let's use a common, architecture-agnostic source of entropy; a
per-cpu prng, seeded at boot-time from the crng. This has a few
benefits:
- We can remove choose_random_kstack_offset(); That was only there to
try to make the timestamp counter value a bit harder to influence
from user space [*].
- The architecture code is simplified. All it has to do now is call
add_random_kstack_offset() in the syscall path.
- The strength of the randomness can be reasoned about independently
of the architecture.
- Arches previously using get_random_u16() now have much faster
syscall paths, see below results.
[*] Additionally, this gets rid of some redundant work on s390 and x86.
Before this patch, those architectures called
choose_random_kstack_offset() under arch_exit_to_user_mode_prepare(),
which is also called for exception returns to userspace which were *not*
syscalls (e.g. regular interrupts). Getting rid of
choose_random_kstack_offset() avoids a small amount of redundant work
for the non-syscall cases.
In some configurations, add_random_kstack_offset() will now call
instrumentable code, so for a couple of arches, I have moved the call a
bit later to the first point where instrumentation is allowed. This
doesn't impact the efficacy of the mechanism.
There have been some claims that a prng may be less strong than the
timestamp counter if not regularly reseeded. But the prng has a period
of about 2^113. So as long as the prng state remains secret, it should
not be possible to guess. If the prng state can be accessed, we have
bigger problems.
Additionally, we are only consuming 6 bits to randomize the stack, so
there are only 64 possible random offsets. I assert that it would be
trivial for an attacker to brute force by repeating their attack and
waiting for the random stack offset to be the desired one. The prng
approach seems entirely proportional to this level of protection.
Performance data are provided below. The baseline is v6.18 with rndstack
on for each respective arch. (I)/(R) indicate statistically significant
improvement/regression. arm64 platform is AWS Graviton3 (m7g.metal).
x86_64 platform is AWS Sapphire Rapids (m7i.24xlarge):
+-----------------+--------------+---------------+---------------+
| Benchmark | Result Class | per-cpu-prng | per-cpu-prng |
| | | arm64 (metal) | x86_64 (VM) |
+=================+==============+===============+===============+
| syscall/getpid | mean (ns) | (I) -9.50% | (I) -17.65% |
| | p99 (ns) | (I) -59.24% | (I) -24.41% |
| | p99.9 (ns) | (I) -59.52% | (I) -28.52% |
+-----------------+--------------+---------------+---------------+
| syscall/getppid | mean (ns) | (I) -9.52% | (I) -19.24% |
| | p99 (ns) | (I) -59.25% | (I) -25.03% |
| | p99.9 (ns) | (I) -59.50% | (I) -28.17% |
+-----------------+--------------+---------------+---------------+
| syscall/invalid | mean (ns) | (I) -10.31% | (I) -18.56% |
| | p99 (ns) | (I) -60.79% | (I) -20.06% |
| | p99.9 (ns) | (I) -61.04% | (I) -25.04% |
+-----------------+--------------+---------------+---------------+
I tested an earlier version of this change on x86 bare metal and it
showed a smaller but still significant improvement. The bare metal
system wasn't available this time around so testing was done in a VM
instance. I'm guessing the cost of rdtsc is higher for VMs.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
Link: https://patch.msgid.link/20260303150840.3789438-3-ryan.roberts@arm.com
Signed-off-by: Kees Cook <kees@kernel.org>
101 lines
2.8 KiB
C
101 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_X86_ENTRY_COMMON_H
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#define _ASM_X86_ENTRY_COMMON_H
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#include <linux/randomize_kstack.h>
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#include <linux/user-return-notifier.h>
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#include <asm/nospec-branch.h>
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#include <asm/io_bitmap.h>
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#include <asm/fpu/api.h>
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#include <asm/fred.h>
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/* Check that the stack and regs on entry from user mode are sane. */
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static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs)
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{
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if (IS_ENABLED(CONFIG_DEBUG_ENTRY)) {
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/*
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* Make sure that the entry code gave us a sensible EFLAGS
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* register. Native because we want to check the actual CPU
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* state, not the interrupt state as imagined by Xen.
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*/
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unsigned long flags = native_save_fl();
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unsigned long mask = X86_EFLAGS_DF | X86_EFLAGS_NT;
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/*
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* For !SMAP hardware we patch out CLAC on entry.
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*/
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if (cpu_feature_enabled(X86_FEATURE_SMAP) ||
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cpu_feature_enabled(X86_FEATURE_XENPV))
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mask |= X86_EFLAGS_AC;
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WARN_ON_ONCE(flags & mask);
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/* We think we came from user mode. Make sure pt_regs agrees. */
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WARN_ON_ONCE(!user_mode(regs));
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/*
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* All entries from user mode (except #DF) should be on the
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* normal thread stack and should have user pt_regs in the
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* correct location.
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*/
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WARN_ON_ONCE(!on_thread_stack());
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WARN_ON_ONCE(regs != task_pt_regs(current));
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}
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}
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#define arch_enter_from_user_mode arch_enter_from_user_mode
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static inline void arch_exit_work(unsigned long ti_work)
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{
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if (ti_work & _TIF_USER_RETURN_NOTIFY)
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fire_user_return_notifiers();
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if (unlikely(ti_work & _TIF_IO_BITMAP))
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tss_update_io_bitmap();
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if (unlikely(ti_work & _TIF_NEED_FPU_LOAD))
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switch_fpu_return();
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}
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static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
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unsigned long ti_work)
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{
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fpregs_assert_state_consistent();
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if (unlikely(ti_work))
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arch_exit_work(ti_work);
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fred_update_rsp0();
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#ifdef CONFIG_COMPAT
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/*
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* Compat syscalls set TS_COMPAT. Make sure we clear it before
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* returning to user mode. We need to clear it *after* signal
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* handling, because syscall restart has a fixup for compat
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* syscalls. The fixup is exercised by the ptrace_syscall_32
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* selftest.
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*
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* We also need to clear TS_REGS_POKED_I386: the 32-bit tracer
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* special case only applies after poking regs and before the
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* very next return to user mode.
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*/
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current_thread_info()->status &= ~(TS_COMPAT | TS_I386_REGS_POKED);
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#endif
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/* Avoid unnecessary reads of 'x86_ibpb_exit_to_user' */
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if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) &&
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this_cpu_read(x86_ibpb_exit_to_user)) {
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indirect_branch_prediction_barrier();
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this_cpu_write(x86_ibpb_exit_to_user, false);
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}
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}
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#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare
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static __always_inline void arch_exit_to_user_mode(void)
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{
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amd_clear_divider();
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}
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#define arch_exit_to_user_mode arch_exit_to_user_mode
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#endif
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