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Intel RDT's CDP feature allows the cache to use a different control value depending on whether the accesses was for instruction fetch or a data access. MPAM's equivalent feature is the other way up: the CPU assigns a different partid label to traffic depending on whether it was instruction fetch or a data access, which causes the cache to use a different control value based solely on the partid. MPAM can emulate CDP, with the side effect that the alternative partid is seen by all MSC, it can't be enabled per-MSC. Add the resctrl hooks to turn this on or off. Add the helpers that match a closid against a task, which need to be aware that the value written to hardware is not the same as the one resctrl is using. Update the 'arm64_mpam_global_default' variable the arch code uses during context switch to know when the per-cpu value should be used instead. Also, update these per-cpu values and sync the resulting mpam partid/pmg configuration to hardware. resctrl can enable CDP for L2 caches, L3 caches or both. When it is enabled by one and not the other MPAM globally enabled CDP but hides the effect on the other cache resource. This hiding is possible as CPOR is the only supported cache control and that uses a resource bitmap; two partids with the same bitmap act as one. Awkwardly, the MB controls don't implement CDP and CDP can't be hidden as the memory bandwidth control is a maximum per partid which can't be modelled with more partids. If the total maximum is used for both the data and instruction partids then then the maximum may be exceeded and if it is split in two then the one using more bandwidth will hit a lower limit. Hence, hide the MB controls completely if CDP is enabled for any resource. Tested-by: Gavin Shan <gshan@redhat.com> Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com> Tested-by: Peter Newman <peternewman@google.com> Tested-by: Zeng Heng <zengheng4@huawei.com> Tested-by: Punit Agrawal <punit.agrawal@oss.qualcomm.com> Tested-by: Jesse Chick <jessechick@os.amperecomputing.com> Cc: Dave Martin <Dave.Martin@arm.com> Cc: Amit Singh Tomar <amitsinght@marvell.com> Reviewed-by: Zeng Heng <zengheng4@huawei.com> Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Co-developed-by: Ben Horgan <ben.horgan@arm.com> Signed-off-by: Ben Horgan <ben.horgan@arm.com> Signed-off-by: James Morse <james.morse@arm.com>
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2025 Arm Ltd. */
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#ifndef __ASM__MPAM_H
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#define __ASM__MPAM_H
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#include <linux/arm_mpam.h>
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#include <linux/bitfield.h>
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#include <linux/jump_label.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <asm/sysreg.h>
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DECLARE_STATIC_KEY_FALSE(mpam_enabled);
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DECLARE_PER_CPU(u64, arm64_mpam_default);
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DECLARE_PER_CPU(u64, arm64_mpam_current);
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/*
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* The value of the MPAM0_EL1 sysreg when a task is in resctrl's default group.
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* This is used by the context switch code to use the resctrl CPU property
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* instead. The value is modified when CDP is enabled/disabled by mounting
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* the resctrl filesystem.
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*/
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extern u64 arm64_mpam_global_default;
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#ifdef CONFIG_ARM64_MPAM
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static inline u64 __mpam_regval(u16 partid_d, u16 partid_i, u8 pmg_d, u8 pmg_i)
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{
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return FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d) |
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FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i) |
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FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d) |
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FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i);
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}
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static inline void mpam_set_cpu_defaults(int cpu, u16 partid_d, u16 partid_i,
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u8 pmg_d, u8 pmg_i)
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{
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u64 default_val = __mpam_regval(partid_d, partid_i, pmg_d, pmg_i);
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WRITE_ONCE(per_cpu(arm64_mpam_default, cpu), default_val);
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}
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/*
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* The resctrl filesystem writes to the partid/pmg values for threads and CPUs,
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* which may race with reads in mpam_thread_switch(). Ensure only one of the old
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* or new values are used. Particular care should be taken with the pmg field as
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* mpam_thread_switch() may read a partid and pmg that don't match, causing this
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* value to be stored with cache allocations, despite being considered 'free' by
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* resctrl.
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*/
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static inline u64 mpam_get_regval(struct task_struct *tsk)
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{
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return READ_ONCE(task_thread_info(tsk)->mpam_partid_pmg);
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}
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static inline void mpam_set_task_partid_pmg(struct task_struct *tsk,
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u16 partid_d, u16 partid_i,
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u8 pmg_d, u8 pmg_i)
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{
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u64 regval = __mpam_regval(partid_d, partid_i, pmg_d, pmg_i);
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WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval);
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}
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static inline void mpam_thread_switch(struct task_struct *tsk)
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{
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u64 oldregval;
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int cpu = smp_processor_id();
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u64 regval = mpam_get_regval(tsk);
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if (!static_branch_likely(&mpam_enabled))
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return;
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if (regval == READ_ONCE(arm64_mpam_global_default))
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regval = READ_ONCE(per_cpu(arm64_mpam_default, cpu));
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oldregval = READ_ONCE(per_cpu(arm64_mpam_current, cpu));
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if (oldregval == regval)
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return;
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write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1);
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if (system_supports_sme())
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write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1);
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isb();
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/* Synchronising the EL0 write is left until the ERET to EL0 */
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write_sysreg_s(regval, SYS_MPAM0_EL1);
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WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval);
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}
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#else
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static inline void mpam_thread_switch(struct task_struct *tsk) {}
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#endif /* CONFIG_ARM64_MPAM */
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#endif /* __ASM__MPAM_H */
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