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a7ed7b9d0e
On arm64, it has been possible for a module's sections to be placed more than 128M away from each other since commit: commit3e35d303ab("arm64: module: rework module VA range selection") Due to this, an ftrace callsite in a module's .init.text section can be out of branch range for the module's ftrace PLT entry (in the module's .text section). Any attempt to enable tracing of that callsite will result in a BRK being patched into the callsite, resulting in a fatal exception when the callsite is later executed. Fix this by adding an additional trampoline for .init.text, which will be within range. No additional trampolines are necessary due to the way a given module's executable sections are packed together. Any executable section beginning with ".init" will be placed in MOD_INIT_TEXT, and any other executable section, including those beginning with ".exit", will be placed in MOD_TEXT. Fixes:3e35d303ab("arm64: module: rework module VA range selection") Cc: <stable@vger.kernel.org> # 6.5.x Signed-off-by: panfan <panfan@qti.qualcomm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20250905032236.3220885-1-panfan@qti.qualcomm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_MODULE_H
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#define __ASM_MODULE_H
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#include <asm-generic/module.h>
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struct mod_plt_sec {
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int plt_shndx;
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int plt_num_entries;
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int plt_max_entries;
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};
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struct mod_arch_specific {
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struct mod_plt_sec core;
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struct mod_plt_sec init;
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/* for CONFIG_DYNAMIC_FTRACE */
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struct plt_entry *ftrace_trampolines;
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struct plt_entry *init_ftrace_trampolines;
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};
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u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs,
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void *loc, const Elf64_Rela *rela,
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Elf64_Sym *sym);
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u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs,
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void *loc, u64 val);
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struct plt_entry {
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/*
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* A program that conforms to the AArch64 Procedure Call Standard
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* (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
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* IP1 (x17) may be inserted at any branch instruction that is
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* exposed to a relocation that supports long branches. Since that
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* is exactly what we are dealing with here, we are free to use x16
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* as a scratch register in the PLT veneers.
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*/
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__le32 adrp; /* adrp x16, .... */
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__le32 add; /* add x16, x16, #0x.... */
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__le32 br; /* br x16 */
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};
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static inline bool is_forbidden_offset_for_adrp(void *place)
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{
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return cpus_have_final_cap(ARM64_WORKAROUND_843419) &&
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((u64)place & 0xfff) >= 0xff8;
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}
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struct plt_entry get_plt_entry(u64 dst, void *pc);
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static inline const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
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const Elf_Shdr *sechdrs,
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const char *name)
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{
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const Elf_Shdr *s, *se;
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const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
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for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
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if (strcmp(name, secstrs + s->sh_name) == 0)
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return s;
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}
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return NULL;
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}
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#endif /* __ASM_MODULE_H */
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