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68 Commits

Author SHA1 Message Date
Bjorn Andersson
c7984dc0a2 pinctrl: qcom: Add test case for TLMM interrupt handling 
While looking at the X1E PDC GPIO interrupts it became clear that we're
lacking a convenient and accessible way to validate if the TLMM
interrupt code performing as expected.

This introduces a kunit-based "hack" that relies on pin bias/pull
configuration to tickle the interrupt logic in non-connected pins to
allow us to evaluate that an expected number of interrupts are
delivered.

The bias/pull configuration is done with mmio accesses directly from the
test code, to avoid having to programmatically acquire and drive the
pinconf interface for the test pin. This limits the scalability of the
code to targets with a particular register layout, but serves our needs
for now.

The pin to be used for testing is specified by the tester using the
"tlmm-test.gpio" module parameter.

Worth mentioning is that some of the test cases currently fails for
GPIOs that is not backed by PDC (i.e. "non-wakeup" GPIOs), as lingering
latched interrupt state is being delivered at IRQ request time.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Link: https://lore.kernel.org/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2025-02-28 09:41:14 +01:00
Otto Pflüger
ff5eb00255 pinctrl: qcom: Add MSM8917 tlmm pinctrl driver 
It is based on MSM8916 driver with the pinctrl definitions from
Qualcomm's downstream MSM8917 driver.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/20241215-msm8917-v9-3-bacaa26f3eef@mainlining.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-12-16 15:15:35 +01:00
Melody Olvera
afe9803e3b pinctrl: qcom: Add sm8750 pinctrl driver 
Add TLMM pinctrl driver to support pin configuration with pinctrl
framework for sm8750 SoC.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/20241112002843.2804490-3-quic_molvera@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-11-13 14:45:58 +01:00
Dmitry Baryshkov
11138a5caa pinctrl: qcom: add support for TLMM on SAR2130P 
Add driver for the pincontrol device as present on the Qualcomm
SAR2130P platform. This is based on the msm-5.10 tree, tag
KERNEL.PLATFORM.1.0.r4-00400-NEO.0.

Co-developed-by: Mayank Grover <groverm@codeaurora.org>
Signed-off-by: Mayank Grover <groverm@codeaurora.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-2-11a1d09a6e5f@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-10-22 14:43:45 +02:00
Jingyi Wang
0c4cd2cc87 pinctrl: qcom: add the tlmm driver for QCS8300 platforms 
Add support for QCS8300 TLMM configuration and control via the
pinctrl framework.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-2-8b8d3957cf1a@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-10-22 14:41:44 +02:00
Lijuan Gao
b698f36a9d pinctrl: qcom: add the tlmm driver for QCS615 platform 
Add support for QCS615 TLMM configuration and control via the
pinctrl framework.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/20240920-add_qcs615_pinctrl_driver-v2-2-e03c42a9d055@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-10-01 16:20:16 +02:00
Sricharan Ramabadhran
968e671ebd pinctrl: qcom: Introduce IPQ5424 TLMM driver 
The IPQ5424 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.

Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/20240927065244.3024604-6-quic_srichara@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-10-01 14:19:11 +02:00
Srinivas Kandagatla
c2e5a25e8d pinctrl: qcom: Introduce SM4250 LPI pinctrl driver 
Add support for the pin controller block on SM4250 Low Power Island.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-26 12:41:07 +02:00
Tengfei Fan
fa7b1fe24e pinctrl: qcom: sm4450: dd SM4450 pinctrl driver 
Add pinctrl driver for TLMM block found in SM4450 SoC.
Can Guo helped out in reviewing the driver.

Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-12-20 12:03:03 +01:00
Rajendra Nayak
05e4941d97 pinctrl: qcom: Add X1E80100 pinctrl driver 
Add initial pinctrl driver to support pin configuration with pinctrl
framework for X1E80100 SoC.

Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231117093921.31968-3-quic_sibis@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-11-24 11:22:12 +01:00
Neil Armstrong
22a4a9ed37 pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driver 
Add Top Level Mode Multiplexer (pinctrl) support for the SM8650 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-3-0e179c368933@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-11-13 15:05:13 +01:00
Krzysztof Kozlowski
c4e4767385 pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS 
Add driver for the pin controller in Low Power Audio SubSystem (LPASS)
of Qualcomm SM8650 SoC.

Notable differences against SM8550 LPASS pin controller:
1. Additional address space for slew rate thus driver uses
   LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different
   register.

2. Two new pin mux functions: qca_swr_clk and qca_swr_data

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231027093615.140656-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-11-13 14:58:02 +01:00
Konrad Dybcio
63f7c8445f pinctrl: qcom: Introduce SM6115 LPI pinctrl driver 
Add support for the pin controller block on SM6115's Low Power Island.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-07-26 11:09:47 +02:00
Krzysztof Kozlowski
be9f6d5638 pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM 
Add driver for pin controller in Low Power Audio SubSystem (LPASS).  The
driver is similar to SM8250 LPASS pin controller, with difference in one
new pin (gpio14) belonging to swr_tx_data.

Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2023-07-24 21:07:04 +02:00
Sricharan Ramabadhran
725d1c8916 pinctrl: qcom: Add IPQ5018 pinctrl driver 
Add pinctrl definitions for the TLMM of IPQ5018.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20230608122152.3930377-5-quic_srichara@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-06-09 09:00:09 +02:00
Rohit Agarwal
0f9367525a pinctrl: qcom: Add SDX75 pincontrol driver 
Add initial Qualcomm SDX75 pinctrl driver to support pin configuration
with pinctrl framework for SDX75 SoC.
While at it, reordering the SDX65 entry.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1684425432-10072-4-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-05-29 11:47:57 +02:00
Devi Priya
c74eef68fd pinctrl: qcom: Add IPQ9574 pinctrl driver 
Add pinctrl definitions for the TLMM of IPQ9574

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Link: https://lore.kernel.org/r/20230316072940.29137-5-quic_devipriy@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-03-19 22:00:47 +01:00
Danila Tikhonov
b915395c9e pinctrl: qcom: Add SM7150 pinctrl driver 
Add pinctrl driver for TLMM block found in SM7150 SoC.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20230311212114.108870-3-danila@jiaxyga.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-03-19 21:51:17 +01:00
Kathiravan T
75dc7e600e pinctrl: qcom: Introduce IPQ5332 TLMM driver 
The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206071217.29313-3-quic_kathirav@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-02-07 15:44:39 +01:00
Krzysztof Kozlowski
5a6ca1f240 pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS 
Add druver for pin controller in Low Power Audio SubSystem (LPASS).  The
driver is similar to SM8450 LPASS pin controller, with differences in
few pin groups (qua_mi2s -> i2s0).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230203174645.597053-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-02-06 12:15:51 +01:00
Yadu MG
4b6b185599 pinctrl: qcom: add the tlmm driver sa8775p platforms 
Add support for Lemans TLMM configuration and control via the pinctrl
framework.

Signed-off-by: Yadu MG <quic_ymg@quicinc.com>
Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com>
[Bartosz: made the driver ready for upstream]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230201150011.200613-3-brgl@bgdev.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-02-01 23:44:49 +01:00
Abel Vesa
fcd26bf51c pinctrl: qcom: Add SM8550 pinctrl driver 
Add pinctrl driver for TLMM block found in SM8550 SoC.

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20221230203637.2539900-3-abel.vesa@linaro.org
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2023-01-09 14:20:52 +01:00
Melody Olvera
51a8f99718 pinctrl: qcom: Add QDU1000/QRU1000 pinctrl driver 
Add pin control driver for the TLMM block found in the QDU1000
and QRU1000 SoC.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20221216230852.21691-3-quic_molvera@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-12-29 02:34:53 +01:00
Richard Acayan
61164d220f pinctrl: qcom: add sdm670 pinctrl 
The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various
features. Add a driver to support it.

Link: de5a12173c%5E%21/#F6
Link: 04f083156d%5E%21/#F22
Link: 54837652e3%5E%21/#F0
Link: f0409b0717%5E%21/#F0
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221014001934.4995-4-mailingradian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-10-17 11:27:28 +02:00
Srinivas Kandagatla
67f40373ee pinctrl: qcom: Add sc8280xp lpass lpi pinctrl driver 
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SC8280XP.

This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.

Hardware setup looks like:

    TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18]

This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113747.9111-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-08-25 14:32:04 +02:00
Srinivas Kandagatla
ec1652fc4d pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver 
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8450.

This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.

Hardware setup looks like:

    TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22]

This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113833.9625-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-08-25 14:29:56 +02:00
Konrad Dybcio
f1a5013f91 pinctrl: qcom: Add SM6375 TLMM driver 
Add a driver to control the TLMM block on SM6375. This is an adapted
version of msm-5.4's pinctrl-blair driver.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-26 09:28:53 +02:00
Stephan Gerhold
4528a0cf79 pinctrl: qcom: Add pinctrl driver for MSM8909 
Make it possible to control pins using the TLMM block in the MSM8909 SoC
by adding the necessary definitions for GPIOs, groups and functions.

The driver is originally taken from the msm-4.9 release [1] from Qualcomm,
but cleaned up significantly with several fixes and clarifications.

[1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-11 10:26:52 +02:00
Srinivasa Rao Mandadapu
120a5f2e54 pinctrl: qcom: Add SC7280 lpass pin configuration 
Add pin control support for SC7280 LPASS LPI.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-04-23 00:04:43 +02:00
Srinivasa Rao Mandadapu
9ce49018c6 pinctrl: qcom: Extract chip specific LPASS LPI code 
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-04-23 00:04:43 +02:00
Bjorn Andersson
c0e4c71a9e pinctrl: qcom: Introduce sc8280xp TLMM driver 
The SC8280XP comes, like all other Qualcomm platforms, with a TLMM
block, so add a driver for it.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220308221132.1423218-2-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-03-15 02:03:46 +01:00
Vinod Koul
4beb02f19c pinctrl: qcom: Add SM8450 pinctrl driver 
This adds pincontrol driver for tlmm block found in SM8450 SoC

This patch is based on initial code downstream by
Elliot Berman <eberman@codeaurora.org>

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211201072434.3968768-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-12-09 03:01:30 +01:00
Vamsi Krishna Lanka
bdbf104f8e pinctrl: qcom: Add SDX65 pincontrol driver 
Add initial Qualcomm SDX65 pinctrl driver to support pin configuration
with pinctrl framework for SDX65 SoC.

Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/13acb3cb36349487dee9745ab040d8f1344d2096.1637048107.git.quic_vamslank@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-11-21 23:48:27 +01:00
Shawn Guo
48e049ef12 pinctrl: qcom: Add QCM2290 pinctrl driver 
It's a porting of pinctrl-scuba driver from CAF msm-4.19 kernel.  The
egpio and wake bits are removed.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923033224.29719-3-shawn.guo@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-09-23 23:13:24 +02:00
Konrad Dybcio
7d74b55afd pinctrl: qcom: Add SM6350 pinctrl driver 
This adds pincontrol driver for tlmm block found in SM6350 SoC

This patch is based on downstream copyleft code.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923161450.15278-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-09-23 23:10:41 +02:00
Iskren Chernev
4b77f1dff5 drivers: qcom: pinctrl: Add pinctrl driver for sm6115 
Based on CAF implementation with egpio/wake_reg support removed.

Similar function names were merged to reduce total number of functions.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210723192352.546902-3-iskren.chernev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-31 23:23:06 +02:00
Konrad Dybcio
41353ae7a1 pinctrl: qcom: Add MDM9607 pinctrl driver 
Add a pinctrl driver to allow for managing SoC pins.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210624191743.617073-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-07-23 17:44:13 +02:00
Martin Botka
0c3ae641a2 drivers: qcom: pinctrl: Add pinctrl driver for sm6125 
This patch adds pinctrl driver for sm6125.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210614172713.558192-2-martin.botka@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-06-18 11:21:45 +02:00
Bjorn Andersson
97423113ec pinctrl: qcom: Add sc8180x TLMM driver 
Add pinctrl driver for the sc8180x TLMM block.

A noteworthy difference from previous TLMM blocks is that the registers
for GPIO 177 through 189 are for some reason offset from the typical
layout. Other than that the driver is same old...

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210126042650.1725176-3-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-02-12 08:52:31 +01:00
Vinod Koul
d5d348a327 pinctrl: qcom: Add SM8350 pinctrl driver 
This adds pincontrol driver for tlmm block found in SM8350 SoC

This patch is based on initial code downstream by Raghavendra.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210205140132.274242-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-02-12 08:50:14 +01:00
Srinivas Kandagatla
6e261d1090 pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver 
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.

This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:

TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]

This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201202163443.26499-3-srinivas.kandagatla@linaro.org
[Add some dependencies]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-12-05 23:36:24 +01:00
Rajendra Nayak
ecb454594c pinctrl: qcom: Add sc7280 pinctrl driver 
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7280 SoC

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1604570192-15057-2-git-send-email-rnayak@codeaurora.org
[Change select PINCTRL_MSM to depends on PINCTRL_MSM]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-11-24 09:37:03 +01:00
Jeevan Shriram
ac43c44a7a pinctrl: qcom: Add SDX55 pincontrol driver 
Add initial Qualcomm SDX55 pinctrl driver to support pin configuration
with pinctrl framework for SDX55 SoC.

[ported from downstream and tidy up]

Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201109062620.14566-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-11-10 15:45:37 +01:00
Vladimir Lypak
0e74abf3a0 pinctrl: qcom: add pinctrl driver for msm8953 
Add inititial pinctrl driver for MSM8953 platform. Compatible SoCs are:
MSM8953, APQ8053, SDM(SDA)450, SDM(SDA)632.
Based off CAF implementation.

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201007160611.942754-1-junak.pub@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-11-10 14:58:14 +01:00
Bartosz Dudziak
db436a7198 pinctrl: qcom: Add msm8226 pinctrl driver. 
Add initial Qualcomm msm8226 pinctrl driver to support pin configuration
with pinctrl framework for msm8226 SoC.

- Initial formatting and style was taken from the msm8x74 pinctrl driver
  added by Björn Andersson <bjorn.andersson@linaro.org>

Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-08-27 10:27:14 +02:00
Venkata Narendra Kumar Gutta
4e3ec9e407 pinctrl: qcom: Add sm8250 pinctrl driver. 
Add initial Qualcomm SM8250 pinctrl driver to support pin configuration
with pinctrl framework for SM8250 SoC.

Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Link: https://lore.kernel.org/r/1586477057-7636-2-git-send-email-vnkgutta@codeaurora.org
[bjorn: Regrouped functions, upstream tiles implementation, dropped
        downstream-only features]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200417061907.1226490-3-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-04-28 11:18:05 +02:00
Sricharan R
ef1ea54eab pinctrl: qcom: Add ipq6018 pinctrl driver 
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq6018.

Co-developed-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Link: https://lore.kernel.org/r/1579439601-14810-3-git-send-email-sricharan@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2020-02-14 11:17:04 +01:00
AngeloGioacchino Del Regno
bcd11493f0 pinctrl: qcom: Add a pinctrl driver for MSM8976 and 8956 
Add the pinctrl driver to support pin configuration with the
pinctrl framework on MSM8976, MSM8956, APQ8056, APQ8076.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191005105936.31216-2-kholk11@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2019-10-16 15:56:18 +02:00
Jitendra Sharma
f2ae04c45b pinctrl: qcom: Add SC7180 pinctrl driver 
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7180

Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
[rnayak: modify to use upstream tile support
	 sort and squash some functions]
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190806060536.18094-2-rnayak@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2019-08-07 14:43:51 +02:00
Prasad Sodagudi
57218371d5 pinctrl: qcom: Add SM8150 pinctrl driver 
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SM8150

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: modify to use upstream tile support
	use upstream code style
	order the functions and squash functions]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2019-07-04 09:47:13 +02:00