Commit Graph
1891 Commits
Author SHA1 Message Date
Anson Huang acc4f98d44 clk: imx6ul: add mmdc1 ipg clock
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 11:15:20 -07:00
Alexandre Belloni d387ff5427 clk: at91: add new DT lookup function
Add a new DT lookup function to lookup for PMC clocks.

Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the
platforms are converted.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17 10:44:33 -07:00
Paul Cercueil 2fdecde775 dt-bindings: clock: Add jz4725b-cgu.h header
This will be used from the devicetree bindings to specify the clocks
that should be obtained from the jz4725b-cgu driver.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:19:43 -07:00
Shefali Jain 652f1813c1 clk: qcom: gcc: Add global clock controller driver for QCS404
Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.

Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Co-developed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bamse, vkoul: rebase and tidyup for upstream]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Lowercase hex]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:13:54 -07:00
Taniya Das f2a76a2955 clk: qcom: Add Global Clock controller (GCC) driver for SDM660
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of
defines to avoid duplicates]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 15:06:43 -07:00
Manivannan Sadhasivam 3b6b13ede0 dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk
Add devicetree bindings for HiSilicon Hi3670 clock controller.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:46:56 -07:00
Manivannan Sadhasivam a35bcf7c7f dt-bindings: reset: Add binding constants for Actions Semi S900 RMU
Add device tree binding constants for Actions Semi S900 SoC Reset
Management Unit (RMU).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:41:15 -07:00
Manivannan Sadhasivam 73a5e67efa dt-bindings: reset: Add binding constants for Actions Semi S700 RMU
Add device tree binding constants for Actions Semi S700 SoC Reset
Management Unit (RMU).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16 14:41:01 -07:00
Krzysztof Kozlowski 40970f7a43 dt-bindings: thermal: samsung: Add SPDX license identifier
Replace GPL license statement with SPDX license identifier (GPL-2.0+).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-10-15 13:35:45 -05:00
Krzysztof Kozlowski cd9102e9ad dt-bindings: clock: samsung: Add SPDX license identifiers
Replace GPL license statements with SPDX license identifiers (GPL-2.0).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-10-15 13:35:00 -05:00
Heiko Stuebner 5f697a0e31 clk: rockchip: add clock-id for HCLK_HDMI on rk3066
RK3066 and RK3188 share most of the clock controller but the rk3066 does
have an internal hdmi encoder and associated clock. Therefore add a
clock-id so that this clock can be used.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-10-11 14:57:25 +02:00
Arnd Bergmann e4c080a10a Merge tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx into next/drivers
arm64: zynqmp: SoC CLK changes for v4.20

This patchset adds CCF compliant clock driver for ZynqMP.
Clock driver queries supported clock information from firmware
and regiters pll and output clocks with CCF.

* tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx:
  drivers: clk: Add ZynqMP clock driver
  dt-bindings: clock: Add bindings for ZynqMP clock driver
  firmware: xilinx: Add zynqmp IOCTL API for device control
  Documentation: xilinx: Add documentation for eemi APIs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-10 13:47:06 +02:00
Arnd Bergmann f7d87826fe Merge tag 'reset-for-4.20' of git://git.pengutronix.de/git/pza/linux into next/drivers
Reset controller changes for v4.20

This adds a new driver for the PDC Global (Power Domain Controller)
reset controller found on Qualcomm SDM845 SoCs, fixes a potential
use-after-free issue in reset_controller_dev.of_xlate() callbacks
from __of_reset_control_get(), and trivially fixes a documentation
grammar issue.

* tag 'reset-for-4.20' of git://git.pengutronix.de/git/pza/linux:
  reset: Fix potential use-after-free in __of_reset_control_get()
  reset: qcom: PDC Global (Power Domain Controller) reset controller
  dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
  reset: Grammar s/more then once/more than once/

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-10 13:41:22 +02:00
Linus Walleij b0b378acde Merge tag 'sh-pfc-for-v4.20-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.20 (take three)

  - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033)
    SoCs,
  - Add INTC-EX pin groups on R-Car E3.
2018-10-10 11:15:33 +02:00
Rajan Vaja 26372d0973 dt-bindings: clock: Add bindings for ZynqMP clock driver
Add documentation to describe Xilinx ZynqMP clock driver
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-09 13:26:34 +02:00
Quentin Schulz 9494a6c2e4 dt-bindings: net: vsc8531: add two additional LED modes for VSC8584
The VSC8584 (and most likely other PHYs in the same generation) has two
additional LED modes that can be picked, so let's add them.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-08 10:31:27 -07:00
Quentin Schulz b68fc09be4 dt-bindings: add constants for Microsemi Ocelot SerDes driver
The Microsemi Ocelot has multiple SerDes and requires that the SerDes be
muxed accordingly to the hardware representation.

Let's add a constant for each SerDes available in the Microsemi Ocelot.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-05 14:36:44 -07:00
Krzysztof Kozlowski 9dbcfe1ace dt-bindings: clock: samsung: Add SPDX license identifiers
Replace GPL license statements with SPDX license identifiers (GPL-2.0).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-10-05 13:36:40 +02:00
Marek Szyprowski fa34efff75 clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock
driver, so support for them in Exynos4-clk driver can be removed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-10-05 13:36:35 +02:00
Leonard Crestez de24832709 reset: imx7: Add PCIE_CTRL_APPS_TURNOFF
This is required for the imx pci driver to send the PME_Turn_Off TLP.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
2018-10-05 09:56:19 +01:00
Sibi Sankar 032f11638f dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
Add PDC Global (Power Domain Controller) binding for SDM845 SoCs.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-10-05 10:33:28 +02:00
Tero Kristo 8fa4509579 dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03 15:02:26 +03:00
Tero Kristo 8cfbdbd969 dt-bindings: clock: am43xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03 15:02:26 +03:00
Tero Kristo e358cf2e6e dt-bindings: clock: am33xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03 15:02:26 +03:00
Phil Edworthy d6381fbbf2 dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentation
The Renesas RZ/N1 device family PINCTRL node description.

Based on a patch originally written by Michel Pollet at Renesas.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-10-02 12:16:39 +02:00
Arnd Bergmann 6a11b1804a Merge tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt
Actions Semi arm64 based SoC DT for v4.20

This updates SPDX headers for remaining files.

For S900 it adds clock, pinctrl, i2c and dma nodes.
S900 SPS is added via topic branch (shared with driver).

For S700 it adds clock nodes.

* tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
  arm64: dts: actions: s700: Set UART clock references from CMU
  arm64: dts: actions: s700: Add Clock Management Unit
  arm64: dts: actions: s900: Add DMA Controller
  arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2
  arm64: dts: actions: s900: Add I2C controller nodes
  arm64: dts: actions: s900-bubblegum-96: Add gpio line names
  arm64: dts: actions: s900: Add gpio properties to pinctrl node
  arm64: dts: actions: s900: Add pinctrl node
  arm64: dts: actions: s900: Add SPS node
  arm64: dts: actions: s900: Source CMU clock for UARTs
  arm64: dts: actions: s900: Add Clock Management Unit nodes
  dt-bindings: power: Add Actions Semi S900 SPS
  arm64: dts: actions: Convert to new-style SPDX license identifiers

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 11:19:36 +02:00
Arnd Bergmann 68b679b339 Merge tag 'actions-drivers+s900-sps-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers
Actions Semi SoC drivers for v4.20 #2

The SPS power domain driver is extended for S900 SoC.
This required merging a topic branch for the new bindings header.

* tag 'actions-drivers+s900-sps-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
  soc: actions: sps: Add S900 power domains
  dt-bindings: power: Add Actions Semi S900 SPS
  soc: actions: Update SPS help text for S700
  soc: actions: Convert to SPDX license identifiers

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 10:02:59 +02:00
Manivannan Sadhasivam d1ca7c56e1 dt-bindings: power: Add Actions Semi S900 SPS
Define power domains for Actions Semi S900 SoC Smart Power System (SPS).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 16:22:50 +02:00
Arnd Bergmann 86e762d967 Merge tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Renesas ARM Based SoC Drivers Updates for v4.20

* Convert to SPDX identifiers
* R-Car V3M (r8a77970) and V3H (r8a77980): Document Timer Unit (TMU) bindings
* RZ/G1N (r8a7744) and RZ/G1C (r8a77470) SoCs:
  - Document APMU and SMP enable method
* RZ/G2M (r8a74a1), RZ/G1N (r8a7744) and RZ/G2E (r8a774c0) SoCs:
  - Add reset support
  - Add sysc support
* RZ/G2M (r8a774a1), RZ/G2E (r8a774c0) and RZ/A2M (r7s9210) SoCs:
  - Add support for identifying SoC
* RZ/A2M (r7s9210) SoC:
  - Add basic SoC setup support

* tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits)
  dt-bindings: apmu: Document r8a7744 support
  dt-bindings: timer: renesas: tmu: document R8A779{7|8}0 bindings
  dt-bindings: apmu: Document r8a77470 support
  soc: renesas: rcar-rst: Add support for RZ/G1N
  dt-bindings: reset: rcar-rst: Document r8a7744 reset module
  soc: renesas: rcar-sysc: Add r8a7744 support
  dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macros
  dt-bindings: power: rcar-sysc: Document r8a7744 SYSC binding
  soc: renesas: rcar-rst: Add support for RZ/G2E
  dt-bindings: reset: rcar-rst: Document r8a774c0 rst
  soc: renesas: rcar-sysc: Add r8a774c0 support
  dt-bindings: power: rcar-sysc: Document r8a774c0 sysc
  dt-bindings: power: Add r8a774c0 SYSC power domain definitions
  soc: renesas: Identify RZ/G2E
  soc: renesas: convert to SPDX identifiers
  soc: renesas: rcar-rst: Add support for RZ/G2M
  soc: renesas: rcar-sysc: Add r8a774a1 support
  dt-bindings: power: Add r8a774a1 SYSC power domain definitions
  soc: renesas: identify RZ/A2
  ARM: shmobile: Add basic RZ/A2 SoC support
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 22:16:58 +02:00
Adam Thomson 63f59b73e8 dt-bindings: connector: Add support for USB-PD PPS APDOs to bindings
Add support for PPS APDOs to connector bindings so a port controller
can specify support for PPS, as per existing FIXED/BATT/VAR PDOs.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-20 12:56:02 +02:00
Fabrizio Castro 0acb6b53df clk: renesas: Add r8a774c0 CPG Core Clock Definitions
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
Clock Outputs, as listed in Table 8.2g ("List of Clocks
[RZ/G2E]") of the RZ/G2 Hardware User's Manual.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 16:41:00 +02:00
Biju Das 6ff9cb53da clk: renesas: Add r8a7744 CPG Core Clock Definitions
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 16:37:56 +02:00
Kuninori Morimoto 5d169ce737 dt-bindings: clock: renesas: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text on Renesas related headers.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 16:33:10 +02:00
Biju Das 841e37a5ca dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macros
Add power domain indices for RZ/G1N (R8A7744) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-17 10:30:37 +02:00
Fabrizio Castro cb391265bc dt-bindings: power: Add r8a774c0 SYSC power domain definitions
This patch adds power domain indices for RZ/G2E.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-14 15:28:41 +02:00
Greg Kroah-Hartman 4b55dce8b0 Merge tag 'iio-for-4.20a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next
Jonathan writes:

1st round of IIO new device support, features and cleanups in the 4.20 cycle.

There is a merge commit in here to pull in regmap support for repeatedly
reading the same register (to read out FIFOs).  Used by the adxl372 driver.
This will find uses elsewhere once we tidy up various drivers that are
effectively doing this and relying on not enabling regcache.

New device support
* Analog devices ADXL372 accelerometer
  - new driver for this accelerometer including fifo and and interrupt support.
    Follow up patches enforce trigger validation, add sampling frequency
    control and filter bandwidth control.  A later series added i2c support
    to the existing SPI support.
* ST lsm6dsx
  - rework and add support fo the LSM6DSO 6 axis mems sensor.
* Linear LTC 1660 DAC
  - new driver supporting the LTC 1660 and LTC 1665 SPI DACs.
* Microchip mcp3911 ADC.
  - new driver for this integrated analog front end and ADC.
* Qualcomm SPMI PMIC5 adc driver
  - using the spmi framework, new driver and bindings for this ADC.
    Follow up patch adds some missing channels.

Features
* ad5758
  - support hard reset using a gpio (if provided).
* mpu6050
  - Regulator support
* qcom-spmi-adc5
  - Sanity check the channel numbers provided by DT to make sure the
    driver actually knows about them.
* sc27xx
  - give raw data for channel 20 as it's used on all known boards for
    the headset which needs a custom converstion function.  If it turns
    out someone builds a board where this isn't true we will deal with it
    when it happens.
  - add ADC scale calibration.
* tsl2772
  - support device tree binding to set the proximity led settings.
  - regulator supprot.
  - binding for apds9930 - trivial addition as register compatible with tsl2772.

Cleanups / Minor fixes

* adxl345
  - supress a static checker warning but explicitly checking if the id
    object is null.
* bh1750
  - avoid CONFIG_PM_SLEEP checks.
  - SPDX.
* bme680
  - spelling mistake
  - use clamp rather than open coding.
  - white space and other similar fixes.
  - rename MSK to MASK for clarifty and use GENMASK to specify them.
  - use the FIELD_GET macro rather than a very odd accessor of dividing by
    16 to get the shift.
  - rework to share handing for oversampling of the various channels in a
    unified way.
  - check explicitly for val2 in write_raw function to ensure it is 0.
  - drop some field defines that don't add anything.
* dpot-adc
  - SPDX
* envelope detector
  - SPDX
* isl29501
  - fix an ancient compiler warning mostly because it results in much
    nicer code.
* max30102
  - mark switch fall throughs.
* max44000
  - drop an unused variable.
* max512
  - avoid CONFIG_PM_SLEEP checks.
* max5481
  - use of_device_get_match_data rather than open coding it.
* max5821
  - avoid CONFIG_PM_SLEEP checks.
* max9611
  - explicity cast an enum to an integer to make it totally clear that
    this is intended.
* mcp4018
  - fix an inconsistent MODULE_LICENSE.
  - use of_device_get_match_data rather than open coding it.
* mcp4531
  - use of_device_get_match_data rather than open coding it.
  - SPDX
* mcp4725
  - avoid CONFIG_PM_SLEEP checks.
* mcp4922
  - Fix error handling and prevent writing a negative to when setting the
    output voltage.
* ms5611
  - drop deprecated compatible strings without manufacturer from being
    explicitly listed.  They are handled anyway.
  - SPDX
* multiplexer
  - SPDX
* qcom-vadc
  - fix inconsistent documentation for reg.
* ti-dac5571
  - provide and of_match_table.

* treewide
  - update Michael Hennerich's email address.
  - Use %pOFn rather than device_node.name.
* documentation.
  - tidy up a wrong kernel version for the introduction of the
    position_relative ABI.
2018-09-14 10:38:48 +02:00
Biju Das 066f7e63b9 dt-bindings: power: Add r8a774a1 SYSC power domain definitions
This patch adds power domain indices for RZ/G2M.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-12 10:18:55 +02:00
Chris Brandt fde35c9c7d clk: renesas: cpg-mssr: Add R7S9210 support
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
Standby.

The Module Standby HW in the RZ/A series is very close to R-Car HW, except
for how the registers are laid out.
The MSTP registers are only 8-bits wide, there are no status registers
(MSTPSR), and the register offsets are a little different. Since the RZ/A
hardware manuals refer to these registers as the Standby Control Registers,
we'll use that name to distinguish the RZ/A type from the R-Car type.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Rob Herring <robh@kernel.org> # DT bits
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:01:07 +02:00
Radu Pirea a785ce4c6d dt-bindings: Add binding for atmel-usart in SPI mode
This patch moves the bindings for serial from serial/atmel-usart.txt to
mfd/atmel-usart.txt and adds bindings for USART in SPI mode.

Signed-off-by: Radu Pirea <radu.pirea@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-09-10 16:07:11 +01:00
Jagan Teki 8b2a378704 dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.

Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-05 09:19:59 +02:00
Amit Nischal f40c467523 dt-bindings: clock: Introduce QCOM Camera clock bindings
Add device tree bindings for camera clock controller for
Qualcomm Technology Inc's SDM845 SoCs.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-30 18:26:45 -07:00
Yixun Lan 3cd3c83f67 pinctrl: Add compatibles for Amlogic Meson G12A pin controllers
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-29 10:34:53 +02:00
Douglas Anderson 48735597f7 clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
These clocks will need to be defined in the clock driver and
referenced in device tree files.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-28 15:56:25 -07:00
Rajendra Nayak b567752144 clk: qcom: Add some missing gcc clks for msm8996
Add a few missing gcc clks for msm8996

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[bjorn: omit aggre0_noc_qosgen_extref_clk]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-28 15:51:44 -07:00
Krzysztof Kozlowski 94047d9795 clk: s2mps11,s3c64xx: Add SPDX license identifiers
Replace GPL v2.0 and v2.0+ license statements with SPDX license
identifiers.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-27 14:17:03 -07:00
Krzysztof Kozlowski f300168a3a clk: max77686: Add SPDX license identifiers
Replace GPL v2.0 and v2.0+ license statements with SPDX license
identifiers.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-27 14:16:51 -07:00
Biju Das 62f32dde33 clk: renesas: Add r8a774a1 CPG Core Clock Definitions
Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-27 17:00:19 +02:00
Aapo Vienamo d9be10edf7 dt-bindings: Add Tegra PMC pad configuration bindings
Document the PMC pinctrl bindings for pad power state and signaling
voltage configuration. Both nvidia,tegra186-pmc.txt and
nvidia,tegra20-pmc.txt are modified as they both cover SoC generations
for which these bindings apply.

Add a header defining Tegra PMC pad voltage configurations.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27 12:21:43 +02:00
Linus Torvalds b326272010 Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late updates from Olof Johansson:
 "A couple of late-merged changes that would be useful to get in this
  merge window:

   - Driver support for reset of audio complex on Meson platforms. The
     audio driver went in this merge window, and these changes have been
     in -next for a while (just not in our tree).

   - Power management fixes for IOMMU on Rockchip platforms, getting
     closer to kexec working on them, including Chromebooks.

   - Another pass updating "arm,psci" -> "psci" for some properties that
     have snuck in since last time it was done"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  iommu/rockchip: Move irq request past pm_runtime_enable
  iommu/rockchip: Handle errors returned from PM framework
  arm64: rockchip: Force CONFIG_PM on Rockchip systems
  ARM: rockchip: Force CONFIG_PM on Rockchip systems
  arm64: dts: Fix various entry-method properties to reflect documentation
  reset: imx7: Fix always writing bits as 0
  reset: meson: add meson audio arb driver
  reset: meson: add dt-bindings for meson-axg audio arb
2018-08-25 14:12:36 -07:00
Olof Johansson c37aad3612 Merge tag 'reset-for-4.19-2' of git://git.pengutronix.de/git/pza/linux into next/late
Reset controller changes for v4.19, part 2

This adds a single new driver for the Amlogic Meson Audio Memory Arbiter
resets.

* tag 'reset-for-4.19-2' of git://git.pengutronix.de/git/pza/linux:
  reset: meson: add meson audio arb driver
  reset: meson: add dt-bindings for meson-axg audio arb

Signed-off-by: Olof Johansson <olof@lixom.net>
2018-08-24 08:49:48 -07:00