5 Commits

Author	SHA1	Message	Date
Vineet Gupta	541366da6a	ARC: [arcompact] Handle bus error from userspace as Interrupt not exception ... Bus errors from userspace on ARCompact based cores are handled by core as a high priority L2 interrupt but current code treated it as interrupt Handling an interrupt like exception is certainly not going to go unnoticed. (and it worked so far as we never saw a Bus error from userspace until IPPK guys tested a DDR controller with ECC error detection etc hence needed to explicitly trigger/handle such errors) - So move mem_service exception handler from common code into ARCv2 code. - In ARCompact code, define mem_service as L2 interrupt handler which just drops down to pure kernel mode and goes of to enqueue SIGBUS Reported-by: Nelson Pereira <npereira@synopsys.com> Tested-by: Ana Martins <amartins@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>	2015-11-14 13:12:20 +05:30
Vineet Gupta	3971cdc202	ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes ... For Run-on-reset, non masters need to spin wait. For Halt-on-reset they can jump to entry point directly. Also while at it, made reset vector handler as "the" entry point for kernel including host debugger based boot (which uses the ELF header entry point) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>	2015-10-28 16:08:17 +05:30
Vineet Gupta	3d5926599a	ARCv2: entry: Fix reserved handler ... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>	2015-08-27 16:25:37 +05:30
Vineet Gupta	4255b07f2c	ARCv2: STAR 9000793984: Handle return from intr to Delay Slot ... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>	2015-06-22 14:06:55 +05:30
Vineet Gupta	1f6ccfff63	ARCv2: Support for ARCv2 ISA and HS38x cores ... The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>	2015-06-22 14:06:55 +05:30