Commit Graph

2114 Commits

Author SHA1 Message Date
Linus Torvalds
2d945dde7f Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
 "This is the usual collection of primarily clk driver updates.

  The big part of the diff is all the new Qualcomm clk drivers added for
  a few SoCs they're working on. The other two vendors with significant
  work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
  to existing drivers and supports some new SoCs while Amlogic is
  starting a significant refactoring to simplify their code.

  The core framework gained a pair of helpers to get the 'struct device'
  or 'struct device_node' associated with a 'struct clk_hw'. Some
  associated KUnit tests were added for these simple helpers as well.

  Beyond that core change there are lots of little fixes throughout the
  clk drivers for the stuff we see every day, wrong clk driver data that
  affects tree topology or supported frequencies, etc. They're not found
  until the clks are actually used by some consumer device driver.

  New Drivers:
   - Global, display, gpu, video, camera, tcsr, and rpmh clock
     controller for the Qualcomm Milos SoC
   - Camera, display, GPU, and video clock controllers for Qualcomm
     QCS615
   - Video clock controller driver for Qualcomm SM6350
   - Camera clock controller driver for Qualcomm SC8180X
   - I3C clocks and resets on Renesas RZ/G3E
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/V2H(P) and RZ/V2N
   - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
   - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
   - Ethernet clocks and resets on Renesas RZ/G3E
   - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
     (R9A09G087) SoCs
   - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
   - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
     RZ/V2N

  Updates:
   - Support atomic PWMs in the PWM clk driver
   - clk_hw_get_dev() and clk_hw_get_of_node() helpers
   - Replace round_rate() with determine_rate() in various clk drivers
   - Convert clk DT bindings to DT schema format for DT validation
   - Various clk driver cleanups and refactorings from static analysis
     tools and possibly real humans
   - A lot of little fixes here and there to things like clk tree
     topology, missing frequencies, flagging clks as critical, etc"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
  clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
  ...
2025-07-31 13:36:27 -07:00
Stephen Boyd
64c21f253a Merge branch 'clk-fixes' into clk-next
Resolve conflicts with i.MX95 changes 88768d6f8c ("clk:
imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx
and aacc875a44 ("clk: imx: Fix an out-of-bounds access in
dispmix_csr_clk_dev_data") in clk-fixes.

* clk-fixes:
  clk: sunxi-ng: v3s: Fix TCON clock parents
  clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
  clk: sunxi-ng: v3s: Fix CSI SCLK clock name
  dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
  clk: scmi: Handle case where child clocks are initialized before their parents
  clk: sunxi-ng: a523: Mark MBUS clock as critical
2025-07-31 09:10:06 -07:00
Linus Torvalds
8be4d31cb8 Merge tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
Pull networking updates from Jakub Kicinski:
 "Core & protocols:

   - Wrap datapath globals into net_aligned_data, to avoid false sharing

   - Preserve MSG_ZEROCOPY in forwarding (e.g. out of a container)

   - Add SO_INQ and SCM_INQ support to AF_UNIX

   - Add SIOCINQ support to AF_VSOCK

   - Add TCP_MAXSEG sockopt to MPTCP

   - Add IPv6 force_forwarding sysctl to enable forwarding per interface

   - Make TCP validation of whether packet fully fits in the receive
     window and the rcv_buf more strict. With increased use of HW
     aggregation a single "packet" can be multiple 100s of kB

   - Add MSG_MORE flag to optimize large TCP transmissions via sockmap,
     improves latency up to 33% for sockmap users

   - Convert TCP send queue handling from tasklet to BH workque

   - Improve BPF iteration over TCP sockets to see each socket exactly
     once

   - Remove obsolete and unused TCP RFC3517/RFC6675 loss recovery code

   - Support enabling kernel threads for NAPI processing on per-NAPI
     instance basis rather than a whole device. Fully stop the kernel
     NAPI thread when threaded NAPI gets disabled. Previously thread
     would stick around until ifdown due to tricky synchronization

   - Allow multicast routing to take effect on locally-generated packets

   - Add output interface argument for End.X in segment routing

   - MCTP: add support for gateway routing, improve bind() handling

   - Don't require rtnl_lock when fetching an IPv6 neighbor over Netlink

   - Add a new neighbor flag ("extern_valid"), which cedes refresh
     responsibilities to userspace. This is needed for EVPN multi-homing
     where a neighbor entry for a multi-homed host needs to be synced
     across all the VTEPs among which the host is multi-homed

   - Support NUD_PERMANENT for proxy neighbor entries

   - Add a new queuing discipline for IETF RFC9332 DualQ Coupled AQM

   - Add sequence numbers to netconsole messages. Unregister
     netconsole's console when all net targets are removed. Code
     refactoring. Add a number of selftests

   - Align IPSec inbound SA lookup to RFC 4301. Only SPI and protocol
     should be used for an inbound SA lookup

   - Support inspecting ref_tracker state via DebugFS

   - Don't force bonding advertisement frames tx to ~333 ms boundaries.
     Add broadcast_neighbor option to send ARP/ND on all bonded links

   - Allow providing upcall pid for the 'execute' command in openvswitch

   - Remove DCCP support from Netfilter's conntrack

   - Disallow multiple packet duplications in the queuing layer

   - Prevent use of deprecated iptables code on PREEMPT_RT

  Driver API:

   - Support RSS and hashing configuration over ethtool Netlink

   - Add dedicated ethtool callbacks for getting and setting hashing
     fields

   - Add support for power budget evaluation strategy in PSE /
     Power-over-Ethernet. Generate Netlink events for overcurrent etc

   - Support DPLL phase offset monitoring across all device inputs.
     Support providing clock reference and SYNC over separate DPLL
     inputs

   - Support traffic classes in devlink rate API for bandwidth
     management

   - Remove rtnl_lock dependency from UDP tunnel port configuration

  Device drivers:

   - Add a new Broadcom driver for 800G Ethernet (bnge)

   - Add a standalone driver for Microchip ZL3073x DPLL

   - Remove IBM's NETIUCV device driver

   - Ethernet high-speed NICs:
      - Broadcom (bnxt):
         - support zero-copy Tx of DMABUF memory
         - take page size into account for page pool recycling rings
      - Intel (100G, ice, idpf):
         - idpf: XDP and AF_XDP support preparations
         - idpf: add flow steering
         - add link_down_events statistic
         - clean up the TSPLL code
         - preparations for live VM migration
      - nVidia/Mellanox:
         - support zero-copy Rx/Tx interfaces (DMABUF and io_uring)
         - optimize context memory usage for matchers
         - expose serial numbers in devlink info
         - support PCIe congestion metrics
      - Meta (fbnic):
         - add 25G, 50G, and 100G link modes to phylink
         - support dumping FW logs
      - Marvell/Cavium:
         - support for CN20K generation of the Octeon chips
      - Amazon:
         - add HW clock (without timestamping, just hypervisor time access)

   - Ethernet virtual:
      - VirtIO net:
         - support segmentation of UDP-tunnel-encapsulated packets
      - Google (gve):
         - support packet timestamping and clock synchronization
      - Microsoft vNIC:
         - add handler for device-originated servicing events
         - allow dynamic MSI-X vector allocation
         - support Tx bandwidth clamping

   - Ethernet NICs consumer, and embedded:
      - AMD:
         - amd-xgbe: hardware timestamping and PTP clock support
      - Broadcom integrated MACs (bcmgenet, bcmasp):
         - use napi_complete_done() return value to support NAPI polling
         - add support for re-starting auto-negotiation
      - Broadcom switches (b53):
         - support BCM5325 switches
         - add bcm63xx EPHY power control
      - Synopsys (stmmac):
         - lots of code refactoring and cleanups
      - TI:
         - icssg-prueth: read firmware-names from device tree
         - icssg: PRP offload support
      - Microchip:
         - lan78xx: convert to PHYLINK for improved PHY and MAC management
         - ksz: add KSZ8463 switch support
      - Intel:
         - support similar queue priority scheme in multi-queue and
           time-sensitive networking (taprio)
         - support packet pre-emption in both
      - RealTek (r8169):
         - enable EEE at 5Gbps on RTL8126
      - Airoha:
         - add PPPoE offload support
         - MDIO bus controller for Airoha AN7583

   - Ethernet PHYs:
      - support for the IPQ5018 internal GE PHY
      - micrel KSZ9477 switch-integrated PHYs:
         - add MDI/MDI-X control support
         - add RX error counters
         - add cable test support
         - add Signal Quality Indicator (SQI) reporting
      - dp83tg720: improve reset handling and reduce link recovery time
      - support bcm54811 (and its MII-Lite interface type)
      - air_en8811h: support resume/suspend
      - support PHY counters for QCA807x and QCA808x
      - support WoL for QCA807x

   - CAN drivers:
      - rcar_canfd: support for Transceiver Delay Compensation
      - kvaser: report FW versions via devlink dev info

   - WiFi:
      - extended regulatory info support (6 GHz)
      - add statistics and beacon monitor for Multi-Link Operation (MLO)
      - support S1G aggregation, improve S1G support
      - add Radio Measurement action fields
      - support per-radio RTS threshold
      - some work around how FIPS affects wifi, which was wrong (RC4 is
        used by TKIP, not only WEP)
      - improvements for unsolicited probe response handling

   - WiFi drivers:
      - RealTek (rtw88):
         - IBSS mode for SDIO devices
      - RealTek (rtw89):
         - BT coexistence for MLO/WiFi7
         - concurrent station + P2P support
         - support for USB devices RTL8851BU/RTL8852BU
      - Intel (iwlwifi):
         - use embedded PNVM in (to be released) FW images to fix
           compatibility issues
         - many cleanups (unused FW APIs, PCIe code, WoWLAN)
         - some FIPS interoperability
      - MediaTek (mt76):
         - firmware recovery improvements
         - more MLO work
      - Qualcomm/Atheros (ath12k):
         - fix scan on multi-radio devices
         - more EHT/Wi-Fi 7 features
         - encapsulation/decapsulation offload
      - Broadcom (brcm80211):
         - support SDIO 43751 device

   - Bluetooth:
      - hci_event: add support for handling LE BIG Sync Lost event
      - ISO: add socket option to report packet seqnum via CMSG
      - ISO: support SCM_TIMESTAMPING for ISO TS

   - Bluetooth drivers:
      - intel_pcie: support Function Level Reset
      - nxpuart: add support for 4M baudrate
      - nxpuart: implement powerup sequence, reset, FW dump, and FW loading"

* tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1742 commits)
  dpll: zl3073x: Fix build failure
  selftests: bpf: fix legacy netfilter options
  ipv6: annotate data-races around rt->fib6_nsiblings
  ipv6: fix possible infinite loop in fib6_info_uses_dev()
  ipv6: prevent infinite loop in rt6_nlmsg_size()
  ipv6: add a retry logic in net6_rt_notify()
  vrf: Drop existing dst reference in vrf_ip6_input_dst
  net/sched: taprio: align entry index attr validation with mqprio
  net: fsl_pq_mdio: use dev_err_probe
  selftests: rtnetlink.sh: remove esp4_offload after test
  vsock: remove unnecessary null check in vsock_getname()
  igb: xsk: solve negative overflow of nb_pkts in zerocopy mode
  stmmac: xsk: fix negative overflow of budget in zerocopy mode
  dt-bindings: ieee802154: Convert at86rf230.txt yaml format
  net: dsa: microchip: Disable PTP function of KSZ8463
  net: dsa: microchip: Setup fiber ports for KSZ8463
  net: dsa: microchip: Write switch MAC address differently for KSZ8463
  net: dsa: microchip: Use different registers for KSZ8463
  net: dsa: microchip: Add KSZ8463 switch support to KSZ DSA driver
  dt-bindings: net: dsa: microchip: Add KSZ8463 switch support
  ...
2025-07-30 08:58:55 -07:00
Stephen Boyd
c30cc9ffc1 Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next
* clk-rockchip:
  clk: rockchip: rk3568: Add PLL rate for 132MHz

* clk-thead:
  clk: thead: th1520-ap: Describe mux clocks with clk_mux
  clk: thead: th1520-ap: Correctly refer the parent of osc_12m
  clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED

* clk-microchip:
  clk: at91: sam9x7: update pll clk ranges

* clk-imx:
  MAINTAINERS: Update i.MX Clock Entry
  clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
  clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
  clk: imx95-blk-ctl: Fix synchronous abort
  dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data

* clk-qcom: (65 commits)
  dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom: Remove double colon from description
  clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Video Clock Controller
  clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos GPU Clock Controller
  clk: qcom: Add Display Clock controller (DISPCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Display Clock Controller
  clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Camera Clock Controller
  clk: qcom: Add Global Clock controller (GCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Global Clock Controller
  clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe
  clk: qcom: gcc-x1e80100: Add missing video resets
  dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
  clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
  clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC
  ...
2025-07-29 15:19:17 -07:00
Stephen Boyd
e3abdd1870 Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next
* clk-renesas: (42 commits)
  clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
  clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
  clk: renesas: r9a09g057: Add XSPI clock/reset
  clk: renesas: r9a09g056: Add XSPI clock/reset
  clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
  clk: renesas: r9a09g057: Add support for xspi mux and divider
  clk: renesas: r9a09g056: Add support for xspi mux and divider
  clk: renesas: r9a09g077: Add RIIC module clocks
  clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
  clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
  clk: renesas: r9a09g057: Add entries for the RSPIs
  dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
  dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
  clk: renesas: rzv2h: Add missing include file
  clk: renesas: rzv2h: Use devm_kmemdup_array()
  clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
  clk: renesas: r9a09g077: Add PCLKL core clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
  dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
  dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
  ...

* clk-samsung:
  clk: samsung: exynosautov920: add block hsi2 clock support
  dt-bindings: clock: exynosautov920: add hsi2 clock definitions
  dt-bindings: clock: exynosautov920: sort clock definitions
  clk: samsung: exynos850: fix a comment
  clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
  clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD

* clk-spacemit:
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  reset: spacemit: add support for SpacemiT CCU resets
  clk: spacemit: mark K1 pll1_d8 as critical
  clk: spacemit: define three reset-only CCUs
  clk: spacemit: set up reset auxiliary devices
  soc: spacemit: create a header for clock/reset registers
  dt-bindings: soc: spacemit: define spacemit,k1-ccu resets

* clk-allwinner:
  clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
  clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
  clk: sunxi-ng: v3s: Fix de clock definition
  clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
  dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset

* clk-amlogic:
  clk: amlogic: s4: remove unused data
  clk: amlogic: drop clk_regmap tables
  clk: amlogic: get regmap with clk_regmap_init
  clk: amlogic: remove unnecessary headers
  clk: amlogic: axg-audio: use the auxiliary reset driver
2025-07-29 15:18:33 -07:00
Linus Torvalds
4df9c0a246 Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
 "These five newly supported chips come with both devicetree
  descriptions and the changes to wire them up to the build system for
  easier bisection.

  The chips in question are:

   - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
     in the product line that started with the Digital StrongARM SA1100
     based PDAs and continued with the Intel PXA2xx that dominated early
     smartphones. This one only made it only into a few products before
     the entire product line was cut in 2015.

   - The QiLai SoC is made by RISC-V core designer Andes Technologies
     and is in the 'Voyager' reference board in MicroATX form factor. It
     uses four in-order AX45MP cores, which is the midrange product from
     Andes.

   - CIX P1 is one of the few Arm chips designed for small workstations,
     and this one uses 12 Cortex-A720/A520 cores, making it also one of
     the only ARMv9.2 machines that one can but at the moment.

   - Axiado AX3000 is an embedded chip with relative small Cortex-A53
     CPU cores described as a "Trusted Control/Compute Unit" that can be
     used as a BMC in servers. In addition to the usual I/O, this one
     comes with 10GBit ethernet and and a 4TOPS NPU.

   - Sophgo SG2000 is an embedded chip that comes with both RISC-V and
     Arm cores that can run Linux. This was already supported for RISC-V
     but now it also works on Arm

  One more chip, the Black Sesame C1200 did not make it in tirm for the
  merge window"

* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  arm64: defconfig: Enable rudimentary Sophgo SG2000 support
  arm64: Add SOPHGO SOC family Kconfig support
  arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
  arm64: dts: sophgo: Add Duo Module 01
  arm64: dts: sophgo: Add initial SG2000 SoC device tree
  MAINTAINERS: Add entry for Axiado
  arm64: defconfig: enable the Axiado family
  arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
  arm64: add Axiado SoC family
  dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
  dt-bindings: serial: cdns: add Axiado AX3000 UART controller
  dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
  dt-bindings: gpio: cdns: convert to YAML
  dt-bindings: arm: axiado: add AX3000 EVK compatible strings
  dt-bindings: vendor-prefixes: Add Axiado Corporation
  MAINTAINERS: Add CIX SoC maintainer entry
  arm64: dts: cix: Add sky1 base dts initial support
  dt-bindings: clock: cix: Add CIX sky1 scmi clock id
  arm64: defconfig: Enable CIX SoC
  mailbox: add CIX mailbox driver
  ...
2025-07-29 11:17:24 -07:00
Linus Torvalds
115e74a29b Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
 "There are a few new variants of existing chips:

   - mt6572 is an older mobile phone chip from mediatek that was
     extremely popular a decade ago but never got upstreamed until now

   - exynos2200 is a recent high-end mobile phone chip used in a few
     Samsung phones like the Galaxy S22

   - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
     (R8A779H0) and used in automotive applications

   - Tegra264 is a new chip from NVIDIA, but support is fairly minimal
     for now, and not much information is public about it

  There are five more chips in a separate branch, as those are new chip
  families that I merged along with the necessary infrastructure.

  New board support is not that exciting, with a total of 33 newly added
  machines here:

   - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
     sg2042

   - Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
     plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
     imx95

   - Two newly added ASPEED BMC based motherboards, and one that got
     removed

   - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
     msm8976 SoCs

   - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1

   - A set-top box based on Amlogic meson-gxm

  Updates for existing machines are spread over all the above families.
  One notable change here is support for the RP1 I/O chip used in
  Raspberry Pi 5"

* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
  riscv: dts: sophgo: fix mdio node name for CV180X
  riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
  dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
  riscv: dts: sophgo: add ethernet GMAC device for sg2042
  riscv: dts: sophgo: Enable ethernet device for Huashan Pi
  riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
  riscv: dts: sophgo: Add ethernet device for cv18xx
  riscv: dts: sophgo: sg2044: add pmu configuration
  riscv: dts: sophgo: sg2044: add ziccrse extension
  riscv: dts: sophgo: add zfh for sg2042
  riscv: dts: sophgo: add ziccrse for sg2042
  riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
  riscv: dts: sophgo: sg2044: add MSI device support for SG2044
  riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
  riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
  dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
  riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
  ...
2025-07-29 11:04:52 -07:00
Arnd Bergmann
7723866e8b Merge tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.17

79b896e7da arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
6516961352 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14

The DB410c D3 camera mezzanine is converted to an overlay.

On MSM8976 SDC2 pinctrl definitions are introduced and BLSP DMA
controller is marked to be managed by another entity.

Add camera subsystem on the QCM2290 platform.

Add and enable remoteproc and related devices on QCS615.

Add and enable Video encoder/decoder on QCS8300 and SA8775P.
Also on SA8775P add CPU OPP tables for scaling DDR/L3 bandwidth based on
CPU frequency, add L3 interconnect definitions, DSI and video
encoder/decoder support.

Enable the SLPI remoteproc on SDM850-based Lenovo Yoga C630.

On SM6350, add the video clock controller, APR and some audio related
services.

Describe the camera subsystem on SM8550 and add Iris video
encoder/decoder node for SM8650.

On SM8750 introduce UFS and Soundwire support, enable these and describe
the sound hardware on MTP and QRD.

Add camera clock controller on SC8180X.

On X Elite, for the Dell XPS13, add WiFi and Bluetooth pwrseq and enable
the fingerprint sensor. For HP Omnibook X14  USB1 SS1 SBU mux and do
some misc cleanup.

Replace the thermal zones inherited from X Elite with X Plus-specific
ones.

Add missing interrupts and clean up unrelated clocks for PCIe
controllers across a variety of platforms.

* tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits)
  arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts
  arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts
  arm64: dts: qcom: x1-asus-zenbook: support sound
  arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes
  arm64: dts: qcom: sm6115: add debug UART pins
  arm64: dts: qcom: sm8650: add iris DT node
  arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
  arm64: dts: qcom: msm8976: Add sdc2 GPIOs
  dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus
  arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely
  arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc
  arm64: dts: qcom: sm8550: Add support for camss
  arm64: dts: qcom: qcs615: disable the CTI device of the camera block
  arm64: dts: qcom: qcs615-ride: enable remoteprocs
  arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
  arm64: dts: qcom: qcs615: Add IMEM and PIL info region
  arm64: dts: qcom: qcs615: Add mproc node for SEMP2P
  arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
  arm64: dts: qcom: sc7180: Expand IMEM region
  arm64: dts: qcom: sdm845: Expand IMEM region
  ...

Link: https://lore.kernel.org/r/20250716031059.76348-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-22 22:19:42 +02:00
Arnd Bergmann
4ec8959278 Merge tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux into soc/dt
RISC-V SpacemiT DT changes for 6.17

- Add DMA translation buses
- Add PWM support
- Add Reset support
- Add eMMC node

* tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux:
  riscv: dts: spacemit: Move eMMC under storage-bus for K1
  riscv: dts: spacemit: Move UARTs under dma-bus for K1
  riscv: dts: spacemit: Add DMA translation buses for K1
  riscv: dts: spacemit: add pwm14_1 pinctrl setting
  riscv: dts: spacemit: add PWM support for K1 SoC
  riscv: dts: spacemit: add reset support for the K1 SoC
  dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
  riscv: dts: spacemit: enable eMMC for K1 SoC

Link: https://lore.kernel.org/r/20250715014214-GYA540030@gentoo
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-22 21:45:12 +02:00
Arnd Bergmann
8fa90d098a Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Updates for v6.17-rc1

Add Tegra264 compatible strings for some core components and extend
bindings where necessary to accomodate the new hardware generation. Also
document some new platforms, for both old and new chips.

* tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T
  dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T
  dt-bindings: Add Tegra264 clock and reset definitions
  dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform
  dt-bindings: rtc: tegra: Document Tegra264 RTC
  dt-bindings: dma: Add Tegra264 compatible string
  dt-bindings: misc: Document Tegra264 APBMISC compatible
  dt-bindings: firmware: Document Tegra264 BPMP
  dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
  dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
  dt-bindings: tegra: pmc: Add Tegra264 compatible
  dt-bindings: memory: tegra: Add Tegra264 support

Link: https://lore.kernel.org/r/20250711220943.2389322-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-22 21:36:28 +02:00
Arnd Bergmann
c5b9bff35a Merge branch 'newsoc/cix-p1' into soc/newsoc
Patches from Peter Chen <peter.chen@cixtech.com>:

Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief
introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview

Currently, to run upstream kernel at Orion O6 board, you need to
use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs.
https://docs.radxa.com/en/orion/o6/bios/install-bios

In this series, we add initial SoC and board support for Kernel building.
Since mailbox is used for SCMI clock communication, mailbox driver is added
in this series for the minimum SoC support.

Patch 1-2: add dt-binding doc for CIX and its sky1 SoC
Patch 3: add Arm64 build support
Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol.
Patch 6: add Arm64 defconfig support
Patch 7-8: add initial dts support for SoC and Orion O6 board
Patch 9: add MAINTAINERS entry

* newsoc/cix-p1:
  MAINTAINERS: Add CIX SoC maintainer entry
  arm64: dts: cix: Add sky1 base dts initial support
  dt-bindings: clock: cix: Add CIX sky1 scmi clock id
  arm64: defconfig: Enable CIX SoC
  mailbox: add CIX mailbox driver
  dt-bindings: mailbox: add cix,sky1-mbox
  arm64: Kconfig: add ARCH_CIX for cix silicons
  dt-bindings: arm: add CIX P1 (SKY1) SoC
  dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21 17:16:16 +02:00
Gary Yang
2b752ae023 dt-bindings: clock: cix: Add CIX sky1 scmi clock id
Add device tree bindings for the scmi clock id on
Cix sky1 platform.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21 17:14:55 +02:00
Arnd Bergmann
31e91dfc7f Merge tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.17 (take two)

  - Add support for the Renesas Gray Hawk Single board with R-Car
    V4M-7 (R8A779H2),
  - Add eMMC and microSD expansion board support for the RZ/V2H and
    RZ/V2N EVK development boards,
  - Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC
    Carrier-II EVK development board,
  - Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK
    development boards,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
  arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
  arm64: dts: renesas: r9a09g057: Add XSPI node
  arm64: dts: renesas: r9a09g056: Add XSPI node
  arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
  arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target
  arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
  arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
  arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
  arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
  arm64: dts: renesas: Add Renesas R8A779H2 SoC support
  arm64: dts: renesas: Factor out Gray Hawk Single board support
  dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock

Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21 17:00:33 +02:00
Peng Fan
0b0cd1857b dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
Add i.MX94 LVDS/DISPLAY CSR compatible string.

Add clock index for the two CSRs.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-1-c1b676ec13be@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2025-07-21 10:33:54 +03:00
Luca Weiss
a4937e9741 dt-bindings: clock: qcom: document the Milos Video Clock Controller
Add bindings documentation for the Milos (e.g. SM7635) Video Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:17:05 -05:00
Luca Weiss
7e5368a14b dt-bindings: clock: qcom: document the Milos GPU Clock Controller
Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:17:05 -05:00
Luca Weiss
63edb206a3 dt-bindings: clock: qcom: document the Milos Display Clock Controller
Add bindings documentation for the Milos (e.g. SM7635) Display Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:17:05 -05:00
Luca Weiss
dbb9d53b71 dt-bindings: clock: qcom: document the Milos Camera Clock Controller
Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:17:05 -05:00
Luca Weiss
95ba6820a6 dt-bindings: clock: qcom: document the Milos Global Clock Controller
Add bindings documentation for the Milos (e.g. SM7635) Global Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:17:04 -05:00
Stephan Gerhold
d0b706509f dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
Add the missing video resets that are needed for the iris video codec.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-4-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:16:15 -05:00
Taniya Das
9c51c66c99 dt-bindings: clock: Add Qualcomm QCS615 Video clock controller
Add DT bindings for the Video clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:12:06 -05:00
Taniya Das
3590dfbdd1 dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller
Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:12:06 -05:00
Taniya Das
8b1750ea00 dt-bindings: clock: Add Qualcomm QCS615 Display clock controller
Add DT bindings for the Display clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:12:06 -05:00
Taniya Das
8df2964990 dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller
Add DT bindings for the Camera clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:12:05 -05:00
Bjorn Andersson
3c4ee2cc7f Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17
Merge the IPQ5018 CMN PLL binding through a topic branch, to allow
merging the clock defines into DeviceTree branch as well.
2025-07-16 23:04:22 -05:00
George Moussalem
314b903c30 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16 23:03:27 -05:00
Thierry Reding
319cc06db4 dt-bindings: Add Tegra264 clock and reset definitions
The BPMP firmware on Tegra264 defines a set of IDs for clock and reset
resources. These are not enumerations but provided by hardware, and 0 is
a reserved value, hence the numbering starts at 1.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-11 16:48:07 +02:00
Jacky Chou
4dc5f7b2c0 dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2
Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to
the ast2600-clock binding header. These are required for proper
reset control of the MAC1 and MAC2 ethernet controllers on the
AST2600 SoC.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://patch.msgid.link/20250709070809.2560688-3-jacky_chou@aspeedtech.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-10 18:13:48 -07:00
Paul Kocialkowski
f45b2949b1 clk: sunxi-ng: v3s: Fix CSI SCLK clock name
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.

Fix the name in the driver, header and device-tree.

Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-By: Icenowy Zheng <uwu@icenowy.me>
Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-03 23:31:04 +08:00
Alex Elder
25a59e813c dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
There are additional SpacemiT syscon CCUs whose registers control both
clocks and resets:  RCPU, RCPU2, and APBC2. Unlike those defined
previously, these will (initially) support only resets.  They do not
incorporate power domain functionality.

Previously the clock properties were required for all compatible nodes.
Make that requirement only apply to the three existing CCUs (APBC, APMU,
and MPMU), so that the new reset-only CCUs can go without specifying them.

Define the index values for resets associated with all SpacemiT K1
syscon nodes, including those with clocks already defined, as well as
the new ones (without clocks).

Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250702113709.291748-2-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-03 22:16:08 +08:00
Geert Uytterhoeven
15bf4a4617 Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17
Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions

Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions
for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared
by driver and DT source files.
2025-07-02 20:53:12 +02:00
Geert Uytterhoeven
8f9ad7670b Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17
Renesas RZ/T2H and RZ/N2H SDHI Clock DT Binding Definitions

SDHI clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and
RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
2025-07-02 20:49:48 +02:00
Lad Prabhakar
2a76193f7c dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02 20:24:10 +02:00
Lad Prabhakar
5e4e8c1415 dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
Add XSPI core clock definitions to the clock bindings for the Renesas
R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI
interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02 20:19:48 +02:00
Geert Uytterhoeven
5701451e84 Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17
Renesas RZ/N2H DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
SoC, shared by driver and DT source files.
2025-06-19 20:19:13 +02:00
Geert Uytterhoeven
a9f57b8d5f Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17
Renesas RZ/T2H PCLKL Clock DT Binding Definition

Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas
RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
2025-06-19 20:11:28 +02:00
Lad Prabhakar
292bf6c5b8 dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC.  The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19 20:08:13 +02:00
Lad Prabhakar
62ab7ac5be dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H
(R9A09G077) SoC.  This clock is used by peripherals such as IIC, WDT,
and others.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19 20:00:55 +02:00
Bjorn Andersson
c1e21ccfe4 Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17
Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.
2025-06-18 17:16:38 -05:00
Luo Jie
0c25ae62f5 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.

Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-18 17:16:26 -05:00
Raghav Sharma
da5cb65d25 dt-bindings: clock: exynosautov920: add hsi2 clock definitions
Add device tree clock binding definitions for CMU_HSI2

Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250529112640.1646740-3-raghav.s@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-12 17:26:57 +02:00
Satya Priya Kakitapalli
b5975ce461 dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller
Add device tree bindings for the camera clock controller on
Qualcomm SC8180X platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10 22:14:31 -05:00
Satya Priya Kakitapalli
19ac3579af dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x
The multi-media AHB clocks are needed to create HW dependency in
the multimedia CC dt blocks and avoid any issues. They were not
defined in the initial bindings. Add all the missing clock bindings
for gcc-sc8180x.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-1-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10 22:14:31 -05:00
Claudiu Beznea
4a59e02a5a dt-bindings: clock: rzg2l: Drop power domain IDs
Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain IDs.  The corresponding code has also been removed.
Currently, there are no device tree users for these IDs.

Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10 10:24:17 +02:00
Geert Uytterhoeven
e5e8a9cce5 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17
Renesas RZ/T2H DT Binding Definitions

DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077)
SoC, shared by driver and DT source files.
2025-06-10 10:23:58 +02:00
Andrea della Porta
7b746d584a dt-bindings: clock: Add RaspberryPi RP1 clock bindings
Add device tree bindings for the clock generator found in RP1 multi
function device, and relative entries in MAINTAINERS file.

Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09 10:10:30 -07:00
Linus Torvalds
ec71f661a5 Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
 "There are 11 newly supported SoCs, but these are all either new
  variants of existing designs, or straight reuses of the existing chip
  in a new package:

   - RK3562 is a new chip based on the old Cortex-A53 core, apparently a
     low-cost version of the Cortex-A55 based RK3568/RK3566.

   - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
     set of on-chip peripherals.

   - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
     family

   - Amlogic S6/S7/S7D

   - Samsung Exynos7870 is an older chip similar to Exynos7885

   - WonderMedia wm8950 is a minor variation on the wm8850 chip

   - Amlogic s805y is almost idential to s805x

   - Allwinner A523 is similar to A527 and T527

   - Qualcomm MSM8926 is a variant of MSM8226

   - Qualcomm Snapdragon X1P42100 is related to R1E80100

  There are also 65 boards, including reference designs for the chips
  above, this includes

   - 12 new boards based on TI K3 series chips, most of them from
     Toradex

   - 10 devices using Rockchips RK35xx and PX30 chips

   - 2 phones and 2 laptops based on Qualcomm Snapdragon designs

   - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses

   - 3 Samsung Galaxy phones based on Exynos7870

   - 5 Allwinner based boards using a variety of ARMv8 chips

   - 9 32-bit machines, each based on a different SoC family

  Aside from the new hardware, there is the usual set of cleanups and
  newly added hardware support on existing machines, for a total of 965
  devicetree changesets"

* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
  MAINTAINERS, mailmap: update Sven Peter's email address
  arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
  arm64: dts: nuvoton: Add pinctrl
  ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
  arm64: dts: blaize-blzp1600: Enable GPIO support
  dt-bindings: clock: socfpga: convert to yaml
  arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3562 pcie unit addresses
  arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
  arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
  arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3576 pcie unit addresses
  arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
  arm64: dts: rockchip: Add missing SFC power-domains to rk3576
  Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
  arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
  arm64: dts: mt6359: Rename RTC node to match binding expectations
  arm64: dts: mt8365-evk: Add goodix touchscreen support
  arm64: dts: mediatek: mt8188: Add missing #reset-cells property
  arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
  ...
2025-05-31 08:08:56 -07:00
Stephen Boyd
63bfd78aae Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-amlogic:
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc

* clk-allwinner:
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  dt-bindings: allwinner: add H616 DE33 clock binding
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: sunxi: Do not enable by default during compile testing
  clk: sunxi-ng: Do not enable by default during compile testing

* clk-rockchip:
  clk: rockchip: rk3528: add slab.h header include
  clk: rockchip: rk3576: add missing slab.h include
  clk: rockchip: rename gate-grf clk file
  clk: rockchip: rename branch_muxgrf to branch_grf_mux
  clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
  clk: rockchip: rk3036: mark ddrphy as critical
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
  clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
  clk: rockchip: Support MMC clocks in GRF region
  dt-bindings: clock: Add GRF clock definition for RK3528
  clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
  clk: rockchip: introduce GRF gates
  clk: rockchip: introduce auxiliary GRFs
  dt-bindings: clock: rk3576: add IOC gated clocks
  clk: rockchip: rk3568: Add PLL rate for 33.3MHz
  clk: rockchip: Drop empty init callback for rk3588 PLL type
  clk: rockchip: rk3588: Add PLL rate for 1500 MHz

* clk-qcom:
  clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
  clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
  clk: qcom: rpmh: make clkaN optional
  clk: qcom: Add support for Camera Clock Controller on QCS8300
  clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
  dt-bindings: clock: add SM6350 QCOM video clock bindings
  clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: Fix missing error check for dev_pm_domain_attach()
2025-05-29 00:30:39 -07:00
Stephen Boyd
3e515fc860 Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next
* clk-socfpga:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables

* clk-sophgo:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

* clk-thead:
  clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
  dt-bindings: clock: thead: Add TH1520 VO clock controller

* clk-samsung:
  clk: samsung: correct clock summary for hsi1 block
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: Use samsung CCF common function
2025-05-29 00:30:28 -07:00
Stephen Boyd
7459da16c9 Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next
* clk-bindings:
  dt-bindings: clock: Drop st,stm32h7-rcc.txt
  dt-bindings: clock: convert bcm2835-aux-clock to yaml
  dt-bindings: clock: Drop maxim,max77686.txt
  dt-bindings: clock: convert vf610-clock.txt to yaml format

* clk-renesas: (26 commits)
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  ...

* clk-spacemit:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

* clk-cleanup:
  clk: test: Forward-declare struct of_phandle_args in kunit/clk.h
  clk: davinci: Use of_get_available_child_by_name()
  clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
  clk: bcm: rpi: Drop module alias
  clk: bcm: kona: Remove unused scaled_div_build
2025-05-29 00:30:17 -07:00