This converts all DaVinci SoCs except DM365 to use new clocksource
driver. DM365 conversion is still under debug and will be part of a
future pull request.
* tag 'davinci-for-v5.4/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: dm646x: Fix a typo in the comment
ARM: davinci: dm646x: switch to using the clocksource driver
ARM: davinci: dm644x: switch to using the clocksource driver
ARM: davinci: dm355: switch to using the clocksource driver
ARM: davinci: move timer definitions to davinci.h
ARM: davinci: da830: switch to using the clocksource driver
ARM: davinci: da850: switch to using the clocksource driver
ARM: davinci: WARN_ON() if clk_get() fails
ARM: davinci: enable the clocksource driver for DT mode
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This pull request contains Broadcom ARM64-based SoCs defconfig updates
for 5.4, please pull the following:
- Nicolas enables the Raspberry Pi CPUFREQ driver in the ARM64 defconfig file
* tag 'arm-soc/for-5.4/defconfig-arm64' of https://github.com/Broadcom/stblinux:
arm64: defconfig: enable cpufreq support for RPi3
This pull request contains Broadcom ARM-based SoCs defconfig updates for
5.4, please pull the following:
- Nicolas enables the Raspberry Pi CPUFREQ driver in both
bcm2835_defconfig and multi_v7_defconfig
* tag 'arm-soc/for-5.4/defconfig' of https://github.com/Broadcom/stblinux:
ARM: defconfig: enable cpufreq driver for RPi
Bitmain SoC changes for v5.4:
Most of the basic infrastructure is completed for BM1880 SoC except
common clock support. We are still couple of patchset away from
booting a distro from eMMC/SD with mainline. Below are the changes
for this cycle:
- Added Reset controller support to BM1880 SoC based on reset-simple
driver.
- Modified pinctrl memory map for BM1880 SoC. The initial pinctrl support
included the PWM registers as a part of the pinctrl memory map. But this
turned out to be useless as PWM registers are not handling any pin muxing
at all. So removed the PWM registers from pinctrl memory map.
* tag 'bitmain-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain:
arm64: dts: bitmain: Modify pin controller memory map
arm64: dts: bitmain: Add reset controller support for BM1880 SoC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Renesas ARM Based SoC Fixes for v5.3
* R-Car D3 (r8a77995) based Draak Board
- Correct backlight regulator name in device tree
* tag 'renesas-fixes-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: renesas: r8a77995: draak: Fix backlight regulator name
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
When in userspace and MSR FP=0 the hardware FP state is unrelated to
the current process. This is extended for transactions where if tbegin
is run with FP=0, the hardware checkpoint FP state will also be
unrelated to the current process. Due to this, we need to ensure this
hardware checkpoint is updated with the correct state before we enable
FP for this process.
Unfortunately we get this wrong when returning to a process from a
hardware interrupt. A process that starts a transaction with FP=0 can
take an interrupt. When the kernel returns back to that process, we
change to FP=1 but with hardware checkpoint FP state not updated. If
this transaction is then rolled back, the FP registers now contain the
wrong state.
The process looks like this:
Userspace: Kernel
Start userspace
with MSR FP=0 TM=1
< -----
...
tbegin
bne
Hardware interrupt
---- >
<do_IRQ...>
....
ret_from_except
restore_math()
/* sees FP=0 */
restore_fp()
tm_active_with_fp()
/* sees FP=1 (Incorrect) */
load_fp_state()
FP = 0 -> 1
< -----
Return to userspace
with MSR TM=1 FP=1
with junk in the FP TM checkpoint
TM rollback
reads FP junk
When returning from the hardware exception, tm_active_with_fp() is
incorrectly making restore_fp() call load_fp_state() which is setting
FP=1.
The fix is to remove tm_active_with_fp().
tm_active_with_fp() is attempting to handle the case where FP state
has been changed inside a transaction. In this case the checkpointed
and transactional FP state is different and hence we must restore the
FP state (ie. we can't do lazy FP restore inside a transaction that's
used FP). It's safe to remove tm_active_with_fp() as this case is
handled by restore_tm_state(). restore_tm_state() detects if FP has
been using inside a transaction and will set load_fp and call
restore_math() to ensure the FP state (checkpoint and transaction) is
restored.
This is a data integrity problem for the current process as the FP
registers are corrupted. It's also a security problem as the FP
registers from one process may be leaked to another.
Similarly for VMX.
A simple testcase to replicate this will be posted to
tools/testing/selftests/powerpc/tm/tm-poison.c
This fixes CVE-2019-15031.
Fixes: a7771176b4 ("powerpc: Don't enable FP/Altivec if not checkpointed")
Cc: stable@vger.kernel.org # 4.15+
Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190904045529.23002-2-gromero@linux.vnet.ibm.com
When we take an FP unavailable exception in a transaction we have to
account for the hardware FP TM checkpointed registers being
incorrect. In this case for this process we know the current and
checkpointed FP registers must be the same (since FP wasn't used
inside the transaction) hence in the thread_struct we copy the current
FP registers to the checkpointed ones.
This copy is done in tm_reclaim_thread(). We use thread->ckpt_regs.msr
to determine if FP was on when in userspace. thread->ckpt_regs.msr
represents the state of the MSR when exiting userspace. This is setup
by check_if_tm_restore_required().
Unfortunatley there is an optimisation in giveup_all() which returns
early if tsk->thread.regs->msr (via local variable `usermsr`) has
FP=VEC=VSX=SPE=0. This optimisation means that
check_if_tm_restore_required() is not called and hence
thread->ckpt_regs.msr is not updated and will contain an old value.
This can happen if due to load_fp=255 we start a userspace process
with MSR FP=1 and then we are context switched out. In this case
thread->ckpt_regs.msr will contain FP=1. If that same process is then
context switched in and load_fp overflows, MSR will have FP=0. If that
process now enters a transaction and does an FP instruction, the FP
unavailable will not update thread->ckpt_regs.msr (the bug) and MSR
FP=1 will be retained in thread->ckpt_regs.msr. tm_reclaim_thread()
will then not perform the required memcpy and the checkpointed FP regs
in the thread struct will contain the wrong values.
The code path for this happening is:
Userspace: Kernel
Start userspace
with MSR FP/VEC/VSX/SPE=0 TM=1
< -----
...
tbegin
bne
fp instruction
FP unavailable
---- >
fp_unavailable_tm()
tm_reclaim_current()
tm_reclaim_thread()
giveup_all()
return early since FP/VMX/VSX=0
/* ckpt MSR not updated (Incorrect) */
tm_reclaim()
/* thread_struct ckpt FP regs contain junk (OK) */
/* Sees ckpt MSR FP=1 (Incorrect) */
no memcpy() performed
/* thread_struct ckpt FP regs not fixed (Incorrect) */
tm_recheckpoint()
/* Put junk in hardware checkpoint FP regs */
....
< -----
Return to userspace
with MSR TM=1 FP=1
with junk in the FP TM checkpoint
TM rollback
reads FP junk
This is a data integrity problem for the current process as the FP
registers are corrupted. It's also a security problem as the FP
registers from one process may be leaked to another.
This patch moves up check_if_tm_restore_required() in giveup_all() to
ensure thread->ckpt_regs.msr is updated correctly.
A simple testcase to replicate this will be posted to
tools/testing/selftests/powerpc/tm/tm-poison.c
Similarly for VMX.
This fixes CVE-2019-15030.
Fixes: f48e91e87e ("powerpc/tm: Fix FP and VMX register corruption")
Cc: stable@vger.kernel.org # 4.12+
Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190904045529.23002-1-gromero@linux.vnet.ibm.com
A helper to find the backing page array based on a virtual address.
This also ensures we do the same vm_flags check everywhere instead
of slightly different or missing ones in a few places.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Currently the generic dma remap allocator gets a vm_flags passed by
the caller that is a little confusing. We just introduced a generic
vmalloc-level flag to identify the dma coherent allocations, so use
that everywhere and remove the now pointless argument.
Signed-off-by: Christoph Hellwig <hch@lst.de>
The arm architecture had a VM_ARM_DMA_CONSISTENT flag to mark DMA
coherent remapping for a while. Lift this flag to common code so
that we can use it generically. We also check it in the only place
VM_USERMAP is directly check so that we can entirely replace that
flag as well (although I'm not even sure why we'd want to allow
remapping DMA appings, but I'd rather not change behavior).
Signed-off-by: Christoph Hellwig <hch@lst.de>
Most dma_map_ops instances are IOMMUs that work perfectly fine in 32-bits
of IOVA space, and the generic direct mapping code already provides its
own routines that is intelligent based on the amount of memory actually
present. Wire up the dma-direct routine for the ARM direct mapping code
as well, and otherwise default to the constant 32-bit mask. This way
we only need to override it for the occasional odd IOMMU that requires
64-bit IOVA support, or IOMMU drivers that are more efficient if they
can fall back to the direct mapping.
Signed-off-by: Christoph Hellwig <hch@lst.de>
CONFIG_ARCH_NO_COHERENT_DMA_MMAP is now functionally identical to
!CONFIG_MMU, so remove the separate symbol. The only difference is that
arm did not set it for !CONFIG_MMU, but arm uses a separate dma mapping
implementation including its own mmap method, which is handled by moving
the CONFIG_MMU check in dma_can_mmap so that is only applies to the
dma-direct case, just as the other ifdefs for it.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> # m68k
parisc is the only architecture that sets ARCH_NO_COHERENT_DMA_MMAP
when an MMU is enabled. AFAIK this is because parisc CPUs use VIVT
caches, which means exporting normally cachable memory to userspace is
relatively dangrous due to cache aliasing.
But normally cachable memory is only allocated by dma_alloc_coherent
on parisc when using the sba_iommu or ccio_iommu drivers, so just
remove the .mmap implementation for them so that we don't have to set
ARCH_NO_COHERENT_DMA_MMAP, which I plan to get rid of.
Signed-off-by: Christoph Hellwig <hch@lst.de>
There is no need to go through dma_common_mmap for the arm-nommu
dma mmap implementation as the only possible memory not handled above
could be that from the per-device coherent pool.
Signed-off-by: Christoph Hellwig <hch@lst.de>
While the default ->mmap and ->get_sgtable implementations work for the
majority of our dma_map_ops impementations they are inherently safe
for others that don't use the page allocator or CMA and/or use their
own way of remapping not covered by the common code. So remove the
defaults if these methods are not wired up, but instead wire up the
default implementations for all safe instances.
Fixes: e1c7e32453 ("dma-mapping: always provide the dma_map_ops based implementation")
Signed-off-by: Christoph Hellwig <hch@lst.de>
arch/arc/Makefile overrides -O2 with -O3. This is the only user of
ARCH_CFLAGS. There is no user of ARCH_CPPFLAGS or ARCH_AFLAGS.
My plan is to remove ARCH_{CPP,A,C}FLAGS after refactoring the ARC
Makefile.
Currently, ARC has no way to enable -Wmaybe-uninitialized because both
-O3 and -Os disable it. Enabling it will be useful for compile-testing.
This commit allows allmodconfig (, which defaults to -O2) to enable it.
Add CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y to all the defconfig files
in arch/arc/configs/ in order to keep the current config settings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Renesas ARM SoC updates for v5.4
- Low-level debugging support for RZ/A2M.
* tag 'renesas-arm-soc-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: debug-ll: Add support for r7s9210
Link: https://lore.kernel.org/r/20190823123643.18799-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The AMD Ryzen gen 3 processors came with a different PCI IDs for the
function 3 & 4 which are used to access the SMN interface. The root
PCI address however remained at the same address as the model 30h.
Adding the F3/F4 PCI IDs respectively to the misc and link ids appear
to be sufficient for k10temp, so let's add them and follow up on the
patch if other functions need more tweaking.
Vicki Pfau sent an identical patch after I checked that no-one had
written this patch. I would have been happy about dropping my patch but
unlike for his patch series, I had already Cc:ed the x86 people and
they already reviewed the changes. Since Vicki has not answered to
any email after his initial series, let's assume she is on vacation
and let's avoid duplication of reviews from the maintainers and merge
my series. To acknowledge Vicki's anteriority, I added her S-o-b to
the patch.
v2, suggested by Guenter Roeck and Brian Woods:
- rename from 71h to 70h
Signed-off-by: Vicki Pfau <vi@endrift.com>
Signed-off-by: Marcel Bocu <marcel.p.bocu@gmail.com>
Tested-by: Marcel Bocu <marcel.p.bocu@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Brian Woods <brian.woods@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: "Woods, Brian" <Brian.Woods@amd.com>
Cc: Clemens Ladisch <clemens@ladisch.de>
Cc: Jean Delvare <jdelvare@suse.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-hwmon@vger.kernel.org
Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
i.MX defconfig update for 5.4:
- Enable pinctrl and clock driver support for i.MX8MN SoC.
- Enable SDMA support for i.MX8MQ and i.MX8MM SoC, including
FW_LOADER_USER_HELPER and FW_LOADER_USER_HELPER_FALLBACK to support
SDMA firmware loading via udev.
- Enable module build of i.MX8 DDR PMU driver and ETNAVIV GPU driver.
- Enable module build of OV5645 camera driver in imx_v6_v7_defconfig.
* tag 'imx-defconfig-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: defconfig: CONFIG_DRM_ETNAVIV=m
ARM: imx_v6_v7_defconfig: Select the OV5645 camera driver
arm64: defconfig: Build imx8 ddr pmu as module
arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
arm64: defconfig: Select CONFIG_PINCTRL_IMX8MN by default
arm64: defconfig: Enable SDMA on i.mx8mq/8mm
Link: https://lore.kernel.org/r/20190825153237.28829-7-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ASPEED defconfig updates for 5.4
- Enable the new AST2600 in multi_v7 and the aspeed_g5 configs.
- Regenerate defconfigs to drop old options
- Clean up network options
* tag 'aspeed-5.4-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
ARM: configs: aspeed_g5: Enable AST2600
ARM: configs: multi_v7: Add ASPEED G6
ARM: configs: aspeed: Refresh defconfigs
ARM: configs: aspeed: Enable commonly used network functionality
Link: https://lore.kernel.org/r/CACPK8XdyWzghA0QPDzA_MK5FYwhT5afqDJHNdhc8mfD2uk8MfQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Allwinner arm64 defconfig changes for 5.4
Two patches to enable the IR receiver and the SPDIF transceiver found on
the Allwinner SoCs.
* tag 'sunxi-config64-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: Enable Sun4i SPDIF module
arm64: defconfig: Enable IR SUNXI option
Link: https://lore.kernel.org/r/24f215ca-f3a8-4497-bf98-9ba1808b37be.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64 defconfig for v5.4
- Add CONFIG_DW_WATCHDOG to support the Designware watchdog driver
* tag 'arm64_defconfig_watchdog_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: defconfig: Enable the DesignWare watchdog
Link: https://lore.kernel.org/r/20190819141659.26414-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM64: hisilicon: defconfig updates for v5.4
- Enable ACPI_APEI_PCIEAER for the hisilicon D06 board to
support PCIe AER error report
* tag 'hisi-arm64-defconfig-for-5.4' of git://github.com/hisilicon/linux-hisi:
arm64: defconfig: Enable CONFIG_ACPI_APEI_PCIEAER
Link: https://lore.kernel.org/r/5D562573.5030604@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
More Ux500 device tree updates for the v5.4 kernel:
- Drop TV-OUT muxgroup from the HREF pin control
- Fix up BU21013 touchpad from Dmitry
- Split of AB8500 config in its own DTSI
- Drop the unused USB regulator config
- Add proper thermal zone for the CPU
* tag 'ux500-dts-v5.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: ux500: Update thermal zone
ARM: dts: ux500: Remove ab8500_ldo_usb regulator from device tree
ARM: dts: ux500: Move ab8500 nodes to ste-ab8500.dtsi
ARM: ux500: improve BU21013 touchpad bindings
ARM: dts: ux500: Drop TV-out muxgroup on HREFs
Link: https://lore.kernel.org/r/CACRpkdZ9Xvx+rg-hFVgG61_i2CdQSs+nZq5FXkkK2-3Ce9ooWg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mvebu dt64 for 5.4 (part 1)
- Add mailbox support on Armada 37xx
- Add cpu clock node needed for CPU freq on Armada 7K/8K
- Enhance CP110 COMPHY support used by PCIe, USB3 and SATA
* tag 'mvebu-dt64-5.4-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
arm64: dts: marvell: Add CP110 COMPHY clocks
arm64: dts: marvell: armada-37xx: add mailbox node
Link: https://lore.kernel.org/r/875zmhzjml.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mvebu dt for 5.4 (part 1)
- Disable the kirkwood RTC that doesn't work on the ts219 board
* tag 'mvebu-dt-5.4-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: kirkwood: ts219: disable the SoC's RTC
Link: https://lore.kernel.org/r/878srdzjpj.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
i.MX arm32 device tree changes for 5.4:
- New board support: ZII i.MX7 RMU2, Kontron i.MX6UL N6310, and
PHYTEC phyBOARD-Segin based on i.MX6ULL.
- A series from Andrey Smirnov to update vf610-zii boards on I2C
pinmux, switch watchdog, GPIO expander IRQ.
- Move GIC node into soc node for i.MX6 SoCs.
- Add OV5645 camera support for imx6qdl-wandboard board.
- Drop unneeded snvs_pwrkey node for imx7d-zii-rpu2 and imx7-colibri.
- Use simple-mfd instead of simple-bus for i.MX6 ANATOP.
- Move the native-mode property inside the display-timings node for
various i.MX25 and i.MX27 boards.
- Add EDMA devices for i.MX7ULP SoC.
- A series from Stefan Riedmueller to update imx6ul-phytec-segin board
on various devices.
- Use OF graph to describe the display for opos6uldev board.
- Misc random updates on i.MX7/6 boards.
* tag 'imx-dt-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (53 commits)
ARM: dts: vf610-zii-scu4-aib: Configure IRQ line for GPIO expander
ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards
ARM: dts: vf610-zii-cfu1: Slow I2C0 down to 100 kHz
ARM: dts: pbab01: correct rtc vendor
ARM: vf610-zii-cfu1: Add node for switch watchdog
ARM: dts: imx6: drop gpmi-nand address and size cells
ARM: dts: imx6: replace simple-bus by simple-mfd for anatop
ARM: dts: imx6qdl-colibri: add phy to fec
ARM: dts: imx7-colibri: add recovery for I2C for iMX7
ARM: dts: imx7-colibri: Add sleep pinctrl to ethernet
ARM: dts: imx7-colibri: prepare module device tree for FlexCAN
ARM: dts: imx7-colibri: disable HS400
ARM: dts: imx7-colibri: make sure module supplies are always on
ARM: dts: imx7d: cl-som-imx7: add compatible for phy
ARM: dts: imx7d: cl-som-imx7: make ethernet work again
ARM: dts: imx6ul: Add csi node
ARM: dts: imx25: mbimxsd25: native-mode is part of display-timings
ARM: dts: apf27dev: native-mode is part of display-timings
ARM: dts: edb7211: native-mode is part of display-timings
ARM: dts: imx27-phytec-phycore-rdk: native-mode is part of display-timings
...
Link: https://lore.kernel.org/r/20190825153237.28829-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
device tree support.
- Add DSP device tree support for i.MX8QXP SoC.
* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8qxp: Add DSP DT node
arm64: dts: imx8mn: Add cpu-freq support
arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
arm64: dts: imx8mn: Add gpio-ranges property
arm64: dts: freescale: Add i.MX8MN dtsi support
clk: imx8: Add DSP related clocks
clk: imx: Add support for i.MX8MN clock driver
clk: imx: Add API for clk unregister when driver probe fail
clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
dt-bindings: imx: Add clock binding doc for i.MX8MN
Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
gpio: updates for v5.4
- use a helper variable for &pdev->dev in gpio-em
- tweak the ifdefs in GPIO headers
- fix function links in HTML docs
- remove an unneeded error message from ixp4xx
- use the optional clk_get in gpio-mxc instead of checking the return value
- a couple improvements in pca953x
- allow to build gpio-lpc32xx on non-lpc32xx targets
dts changes for omap variants for v5.4
Remove regulator-boot-off properties that we never had in the mainline
kernel so they won't do anything. We add stdout-path for gta04, and
make am335x-boneblue use am335x-osd335x-common.dtsi file.
* tag 'omap-for-v5.4/dt-take2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-boneblue: Use of am335x-osd335x-common.dtsi
ARM: dts: gta04: define chosen/stdout-path
ARM: dts: omap3-n950-n9: Remove regulator-boot-off property
ARM: dts: am335x-cm-t335: Remove regulator-boot-off property
Link: https://lore.kernel.org/r/pull-1566599057-142651@atomide.com-2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Allwinner DT changes for 5.4
Our usual pile of patches for the next release, which include mostly:
- More fixes thanks to the DT validation using the YAML bindings
- IR receiver support on the H6
- SPDIF support on the H6
- I2C Support on the H6
- CSI support on the A20
- RTC support on the H6
- New Boards: Lichee Zero Plus, Tanix TX6, A64-Olinuxino-eMMC
* tag 'sunxi-dt-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (40 commits)
arm64: dts: allwinner: orange-pi-3: Enable WiFi
ARM: dts: sunxi: Add missing watchdog clocks
ARM: dts: sunxi: Add missing watchdog interrupts
arm64: dts: allwinner: h6: Add support for RTC and fix the clock tree
ARM: dts: sun7i: Add CSI0 controller
arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)
dt-bindings: arm: sunxi: Add compatible for A64 OlinuXino with eMMC
ARM: dts: v3s: Change the timers compatible
ARM: dts: h3: Change the timers compatible
ARM: dts: a83t: Change the timers compatible
ARM: dts: a23/a33: Change the timers compatible
ARM: dts: sun6i: Add missing timers interrupts
ARM: dts: sun5i: Add missing timers interrupts
ARM: dts: sun4i: Add missing timers interrupts
dt-bindings: mfd: Convert Allwinner GPADC bindings to a schema
arm64: dts: allwinner: h6: Introduce Tanix TX6 board
dt-bindings: arm: sunxi: Add compatible for Tanix TX6 board
arm64: allwinner: h6: add I2C nodes
dt-bindings: i2c: mv64xxx: Add compatible for the H6 i2c node.
ARM: dts: sunxi: Add mdio bus sub-node to GMAC
...
Link: https://lore.kernel.org/r/d97e6252-9dd7-4cf5-a3cf-56f78b0ca455.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Optimize modulo operation instruction generation by
using single MSUB instruction vs MUL followed by SUB
instruction scheme.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
This adds support for generating bpf line info for JITed programs
like commit 6f20c71d85 ("bpf: powerpc64: add JIT support for bpf
line info") does for powerpc, but it should pass the array starting
from 1. This fixes test_btf.
Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
If that's not the last reference, d_delete() will do d_drop().
If it is, dput() immediately after it will unhash the sucker
anyway, since ->d_delete() the method is always_delete_dentry().
IOW, there's no point trying to turn it into a negative hashed
dentry - it won't stick around anyway. Just d_drop() it and be
done with that.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
_CACHE_CACHABLE_NONCOHERENT is defined as 3<<_CACHE_SHIFT by default, so
there's no need to define it as such specifically for Loongson.
_CACHE_CACHABLE_COHERENT is not used anywhere in the kernel, so there's
no need to define it at all.
Finally the comment found alongside these definitions seems incorrect -
it suggests that we're defining _CACHE_CACHABLE_NONCOHERENT such that it
actually provides coherence, but the opposite seems to be true & instead
the unused _CACHE_CACHABLE_COHERENT is defined as the typically
incoherent value.
Delete the whole thing, which will have no effect on the compiled code
anyway.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: linux-mips@vger.kernel.org
