Add a USB2 ChipIdea driver for ci13xxx, with optional PHY, clock
and DMA mask, to support USB2 ChipIdea controllers that don't need
specific functions.
Tested on the Marvell Berlin SoCs USB controllers.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The generic plaftorm device for ChipIdea drivers is probed by calling
ci_hdrc_probe. The device structure used is not the one of the specific
ChipIdea driver but the one of the generic ChipIdea platform device.
This results in not being able to probe the PHYs as we're not using the
right device structure. Since all ChipIdea drivers are retrieving their
PHYs in their specific driver code, this didn't impact any of them yet.
Fixes it using the right device structure (dev->parent).
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The core driver has already done it, besides, move set driver data
operation just after ci has allocated successfully in case some
code (like ci_role_start) want to access this driver data.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The hw_device_reset is dedicated to be used at device mode initializaiton,
so delete the parameter 'mode'. For host driver, the ehci driver will
handle all things.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add controller reset API, currently it is used for device mode only.
It may be used for host/otg driver in future.
Ususally, we need this API for dual-role switch and back from hibernation
suspend to let the controller at default state.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Now, USB PHY is mandatory for chipidea core, the flag
CI_HDRC_REQUIRE_TRANSCEIVER is useless.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The phy needs some delay to output the stable status from low
power mode. And for OTGSC, the status inputs are debounced
using a 1 ms time constant, so, delay 2ms for controller to get
the stable status(like vbus and id) when the phy leaves low power.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The individual PHY driver should take this responsibility if it
needs to delay between clear portsc.phcd and let the phy leave
low power mode.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
If 'evdo' property is not defined, then reading the MX25_USB_PHY_CTRL_OFFSET
register is an unneeded operation.
Move the reading of MX25_USB_PHY_CTRL_OFFSET inside the 'evdo' if block code,
where it is actually used.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Some VF drivers use the upper byte of "param1" (the qp count field)
in mlx4_qp_reserve_range() to pass flags which are used to optimize
the range allocation.
Under the current code, if any of these flags are set, the 32-bit
count field yields a count greater than 2^24, which is out of range,
and this VF fails.
As these flags represent a "best-effort" allocation hint anyway, they may
safely be ignored. Therefore, the PF driver may simply mask out the bits.
Fixes: c82e9aa0a8 "mlx4_core: resource tracking for HCA resources used by guests"
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Our boot agent may have left the switch in an certain configuration
state, make sure we issue a software reset prior to configuring the
switch in order to ensure the HW is in a consistent state, in particular
transmit queues and internal buffers.
Fixes: 246d7f773c ("net: dsa: add Broadcom SF2 switch driver")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
In case we fail to ioremap() one of our registers, we would be leaking
existing mappings, unwind those accordingly on errors.
Fixes: 246d7f773c ("net: dsa: add Broadcom SF2 switch driver")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Adjust the number of rpmsg buffers to rely on the size of the
vring, instead of using the hard coded value of 512 (256 per
direction).
This is needed when small vrings are being used, where 256
buffers are too much to fit in a vring.
While considering the vring size, keep using the 512 hard coded
value as an upper limit to avoid wacky resource tables consuming
unreasonable amount of memory.
NOTE: The number of buffers is already assumed to be symmetrical
in each direction, and that logic is unchanged.
Signed-off-by: Suman Anna <s-anna@ti.com>
[edit commit message, small code and comment simplification]
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
The interrupt translation is driven by a set of tables (device,
ITT, and collection) to be in the end delivered to a CPU. Also,
the redistributors rely on a couple of tables (configuration, and
pending) to deliver the interrupts to the CPUs.
This patch adds the required allocators for these tables.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1416839720-18400-8-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Amlogic Meson SoCs include a infrared remote control receiver that can
operate in two modes: "NEC" mode in which the hardware decodes frames
using the NEC IR protocol, and "general" mode in which the receiver
simply reports the duration of pulses and spaces for software
decoding.
This is a driver for the IR receiver that implements software decoding
of received frames.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
The commit, mmc: omap: clarify DDR timing mode between SD-UHS and eMMC,
switched omap_hsmmc to support MMC DDR mode instead of UHS DDR50 mode.
Add UHS DDR50 mode again and this time let's also keep the MMC DDR mode.
Fixes: 5438ad95a5 (mmc: omap: clarify DDR timing mode between SD-UHS and eMMC)
Reported-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
According to the SD card spec, Add a manual tuning command function
for SDR104/HS200.
Sending command 19 or command 21 to read data and compare with the
tunning block pattern.
This patch will help to decrease some platform private codes in SDHCI
platform_execute_tuning() callbacks.
Signed-off-by: Minda Chen <Minda.Chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Voltage Switch Procedure
This patch is to fix an issue found on mb86s7x platforms.
[symptom]
There are some UHS-1 SD memory cards sometimes cannot be detected correctly,
e.g., Transcend 600x SDXC 64GB UHS-1 memory card.
During Signal Voltage Switch Procedure, failure to switch is indicated
by the card holding DAT[3:0] low.
[analysis]
According to SD Host Controller Simplified Specification Version 3.00
chapter 3.6.1, the Signal Voltage Switch Procedure should be:
(1) Check S18A; (2) Issue CMD11; (3) Check CMD 11 response;
(4) Stop providing SD clock; (5) Check DAT[3:0] should be 0000b;
(6) Set 1.8V Signal Enable; (7) Wait 5ms; (8) Check 1.8V Signal Enable;
(9) Provide SD Clock; (10) Wait 1ms; (11) Check DAT[3:0] should be 1111b;
(12) error handling
With CONFIG_MMC_CLKGATE=y, sometimes there is one more gating/un-gating
SD clock between (2) and (3). In this case, some UHS-1 SD cards will hold
DAT[3:0] 0000b at (11) and thus fails Signal Voltage Switch Procedure.
[solution]
By mmc_host_clk_hold() before CMD11, the additional gating/un-gating
SD clock between (2) and (3) can be prevented and thus no failure at (11).
It has been verified with many UHS-1 SD cards on mb86s7x platforms and
works correctly.
Signed-off-by: Vincent Yang <Vincent.Yang@tw.fujitsu.com>
Reviewed-by: Johan Rudholm <jrudholm@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
If platform_get_irq() fails, it is better to propagate the real error value
instead of a 'fake' one.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
devm_ioremap_resource() already checks if 'iores' is NULL or not, so we can
skip this manual check.
While at it, move platform_get_resource() closer to devm_ioremap_resource() for
better readability.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Add support for the DW MMC host found on the Imagination Pistachio SoC.
Like the DW MMC hosts found on SOCFPGA and Rockchip SoCs, the DW MMC
host on Pistachio requires the use of SDMMC_CMD_USE_HOLD_REG.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Instead of registering the irq name with the driver's name, it's better to pass
the device name so that we have a more explicit indication as to what mmc
instance the irq is related:
$ cat /proc/interrupts
CPU0
...
26: 6 - 96 80010000.ssp
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Commit f1d2736c81 (mmc: dw_mmc: control card read threshold) added
dw_mci_ctrl_rd_thld() with an unconditional write to the CDTHRCTL
register at offset 0x100. However before version 240a, the FIFO region
started at 0x100, so the write messes with the FIFO and completely
breaks the driver.
If the version id < 240A, return early from dw_mci_ctl_rd_thld() so as
not to hit this problem.
Fixes: f1d2736c81 (mmc: dw_mmc: control card read threshold)
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.13+
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
We check for NULL pointers after dereferencing so it's too late. Oddly
enough, Smatch misses this code but complains about the caller passing
NULL pointers to this function:
drivers/mmc/host/toshsd.c:389 toshsd_irq()
error: we previously assumed 'host->cmd' could be null (see line 349)
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
