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Author SHA1 Message Date
Giulio Benetti
982f944ed7 drm/panel: add panel CDTech S070WV95-CT16 to panel-simple 
This patch adds support for CDTech S070WV95-CT16 800x480 7" panel to DRM
simple panel driver.

Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180730231117.5631-3-giulio.benetti@micronovasrl.com
 2018-09-27 13:57:00 +02:00
Giulio Benetti
21295ceacf dt-bindings: Add vendor prefix for CDTech(H.K.) Electronics Limited 
This adds a vendor prefix "cdtech" for CDTech(H.K.) Electronics Limited

Website: www.cdtech-lcd.com

Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180730231117.5631-2-giulio.benetti@micronovasrl.com
 2018-09-27 13:56:47 +02:00
Fabio Estevam
db2b0e5ffc drm/panel: seiko-43wvf1g: Add missing ">" character in author's email 
There is a missing ">" character in Marco's email.

Fix it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1532575167-14754-2-git-send-email-festevam@gmail.com
 2018-09-27 13:55:20 +02:00
Fabio Estevam
6bf18d84f7 drm/panel: seiko-43wvf1g: Switch to SPDX identifier 
Adopt the SPDX license identifier headers to ease license compliance
management.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1532575167-14754-1-git-send-email-festevam@gmail.com
 2018-09-27 13:53:11 +02:00
Andrzej Hajda
e077e2f5f8 drm/panel: simple: fix BOE/HV070WSA-100 timings 
Panel timings were taken from vendor code and are not fully correct -
refresh rate is about 50Hz instead of 60Hz. The patch fixes it.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180725154644.25412-9-a.hajda@samsung.com
 2018-09-27 13:51:28 +02:00
Hans de Goede
1f0eb8b810 drm: panel-orientation-quirks: Add quirk for GPD win2 
GPD has done it again, make a nice device (good), use way too generic
DMI strings (bad) and use a portrait screen rotated 90 degrees (ugly).

Because of the too generic DMI strings this entry is also doing bios-date
matching, so the gpd_win2 data struct may very well need to be updated
with some extra bios-dates in the future.

Reported-and-tested-by: russianneuromancer@ya.ru
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180909133457.10636-3-hdegoede@redhat.com
 2018-09-27 13:41:07 +02:00
Arnd Bergmann
064b06bbf1 drm/imx: fix build failure without CONFIG_DRM_FBDEV_EMULATION 
The variable is declared in an #ifdef section, but the user is
now unconditional, which leads to a build failure:

drivers/gpu/drm/imx/imx-drm-core.c: In function 'imx_drm_bind':
drivers/gpu/drm/imx/imx-drm-core.c:264:6: error: 'legacyfb_depth' undeclared (first use in this function); did you mean 'lockdep_depth'?

Remove the remaining #ifdef as well.

Fixes: f53705fd98 ("drm/imx: Use drm_fbdev_generic_setup()")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180926193846.2490574-1-arnd@arndb.de
 2018-09-27 13:13:45 +02:00
Alexandre Belloni
52bf4a900d clocksource/drivers/timer-atmel-pit: Properly handle error cases 
The smatch utility reports a possible leak:

smatch warnings:
drivers/clocksource/timer-atmel-pit.c:183 at91sam926x_pit_dt_init() warn: possible memory leak of 'data'

Ensure data is freed before exiting with an error.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
 2018-09-27 12:01:45 +02:00
Heiko Stuebner
4f297df89d drm/rockchip: vop: add rk3188 hs_start interrupt as dsp_hold equivalent 
The hs_start interrupt on rk3188 fires at the start of a new frame, so
serves essentially the same purpose as the dsp_hold_valid irq in checking
when the last frame got delivered when going to standby. So define it
to fix a hang on atomic_disable of the vop because the completion never
really completed before.

Fixes: 428e15cc41 ("drm/rockchip: vop: add rk3188 vop definitions")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180923123730.14706-1-heiko@sntech.de
 2018-09-27 11:39:32 +02:00
Thomas Zimmermann
9cb5f4873b drm/atmel-hlcdc: Replace drm_dev_unref with drm_dev_put 
This patch unifies the naming of DRM functions for reference counting
of struct drm_device. The resulting code is more aligned with the rest
of the Linux kernel interfaces.

Signed-off-by: Thomas Zimmermann <contact@tzimmermann.org>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180701132415.10161-1-contact@tzimmermann.org
 2018-09-27 11:04:18 +02:00
Jernej Skrabec
c2b70ffcd3 dt-bindings: display: sun4i-drm: Add R40 mixer compatibles 
R40 DE2 mixers are similar to those found in A83T, except it needs
different clock settings.

Add a compatibles for them.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-14-jernej.skrabec@siol.net
 2018-09-27 04:35:42 -04:00
Chen-Yu Tsai
3dcf0f306d Revert "drm/sun4i: Remove R40 display pipeline compatibles" 
This reverts commit 3510e7a7f9.

During the 4.19 merge window for drm-misc, two patches critical to
supporting the display pipeline on the Allwinner R40 SoC were missed.
They were applied later but missed the merge window deadline. As a
result 4.19-rc1 kernel would crash on the R40 when it couldn't parse
the new device tree structure. We ended up removing support for the
R40 display pipeline for 4.19.

Since the missing patches are already merged for 4.20, we can now
revert the commit that removed support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180921142743.8711-1-wens@csie.org
 2018-09-27 04:18:07 -04:00
Sean Paul
7b76d05884 Merge drm/drm-next into drm-misc-next 
Backmerging 4.19-rc5 to pick up sun4i fix

Signed-off-by: Sean Paul <seanpaul@chromium.org>
 2018-09-27 02:54:54 -04:00
Alex Deucher
d30e63b159 drm/amdgpu/vcn: whitespace cleanup 
Fix some indentation issues.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:26 -05:00
Alex Deucher
81bb773f35 drm/amdgpu/soc15: fix warnings in register macro 
expects argument of type ‘unsigned int’ has type ‘long int’

Fixes: 52e211c1f0 ("drm/amdgpu:Add error message when register failed to reach expected value")
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:26 -05:00
James Zhu
a3716d3a06 drm/amdgpu:Enable DPG mode on PCO 
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:25 -05:00
James Zhu
bd5d5180db drm/amdgpu:Add DPG pause mode support 
Add functions to support VCN DPG pause mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:25 -05:00
James Zhu
0b8690b7a8 drm/amdgpu:Add DPG pause state 
Add DPG pause state to support VCN DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:25 -05:00
James Zhu
63e9bb1d98 drm/amdgpu:Add DPG mode support for vcn 1.0 
Add DPG mode start/stop/mc_resume/clock_gating to
support vcn 1.0 DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:24 -05:00
James Zhu
03d6e3aac8 drm/amdgpu:Add DPG mode read/write macro 
Some registers read/write needs program through SDRAM pool under
DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:24 -05:00
James Zhu
f28ff06210 drm/amdgpu:Add DPG support flag 
Add DPG support flag for VCN DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:23 -05:00
James Zhu
b604545b92 drm/amdgpu:Add new register offset/mask to support VCN DPG mode 
New register offset/mask need to be added to support VCN DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:23 -05:00
James Zhu
21cbe2f38c drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test 
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers
can't be directly accessed under DPG(Dynamic Power Gate) mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:23 -05:00
Christian König
1ffdeca648 drm/amdgpu: move more defines into amdgpu_irq.h 
Everything that isn't related to the IH ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:22 -05:00
Christian König
1f8969463b drm/amdgpu: move more interrupt processing into amdgpu_irq.c 
Add a callback to amdgpu_ih_process to remove most of the IV logic.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:22 -05:00
Andrey Grodzovsky
95d7fc4a41 drm/amdgpu: Move fence SW fallback warning v3 
Only print the warning if there was actually some fence processed
from the SW fallback timer.

v2: Add return value to amdgpu_fence_process to let
amdgpu_fence_fallback know fences were actually
processed and then print the warning.

v3: Always return true if seq != last_seq

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:21 -05:00
Christian König
425c31437f drm/amdgpu: cleanup amdgpu_ih.c 
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:21 -05:00
Christian König
f54b30d70b drm/amdgpu: make function pointers mandatory 
We always want those to be setup correctly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:21 -05:00
Christian König
0dd1e5bbec drm/amdgpu: drop extra newline in amdgpu_iv trace 
That is superflous here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:20 -05:00
Huang Rui
7598627621 drm/amdgpu: fix the page fault of raven2 
While the apg_end address is 0xffffffff, if add 1 with it, the value will be
overflow and roll back to 0. So when 0 is written to
mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And
so any access to vram will trigger a page fault.

Raven2's HW issue only need increase the vram end address, and needn't do it on
the agp.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:20 -05:00
Rex Zhu
d355f149d0 drm/amd/pp: Disable dpm features on smu7/8 when suspend 
Need to disable dpm features before halt rlc.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:19 -05:00
Rex Zhu
722ca51d4f drm/amdgpu: Remove redundant code in gfx_v8_0.c 
the CG related registers have been programed in golden setting
PG register default value is 0.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hang Zhou <hang.zhou@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:19 -05:00
Rex Zhu
5d944aaa3c drm/amdgpu: Halt rlc/cp in rlc_safe_mode 
before halt rlc/cp, need to
1. enter rlc safe mode
2. wait rlc/cp idle

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hang Zhou <hang.zhou@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:19 -05:00
Rex Zhu
434e6df2f7 drm/amdgpu: Refine function name 
change function name gfx_v6/7/8/9_0_gpu_init to
gfx_v6/7/8/9_0_constants_init.
this function is just for init gfx constants such
as max pipes, render backends...

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:18 -05:00
Andrey Grodzovsky
3547e3cf19 drm/amdgpu: Deactivate SW interrupt fallback in amdgpu_fence_process v2 
Deactivate SW interrupt fallback when all emited fences are completed.
Also switch interrupt SW fallback message from INFO to WARN.

v2: shorten the warning message a bit and only re-activate the timer during
processing if it was already activated before. (Christian)

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Suggested-by: Christian Konig <Christian.Koenig@amd.com>
Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:18 -05:00
Shaoyun Liu
22a3a2941b drm/amdkfd: Vega20 bring up on amdkfd side 
Add Vega20 device IDs, device info and enable it in KFD.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
 2018-09-26 21:09:18 -05:00
Shaoyun Liu
ba0f2841d5 drm/amdgpu: Add vega20 support on kfd probe 
Add Vega20 support in amdgpu_amdkfd_device_probe.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
 2018-09-26 21:09:17 -05:00
Shaoyun Liu
e715c6d0ea drm/amd: Interface change to support 64 bit page_table_base 
amdgpu_gpuvm_get_process_page_dir should return the page table address
in the format expected by the pm4_map_process packet for all ASIC
generations.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:17 -05:00
Shaoyun Liu
d50941892e drm/amdkfd: Make the number of SDMA queues variable 
Vega20 supports 8 SDMA queues per engine

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:16 -05:00
Emily Deng
a2a8fb512e drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10 
Correct the format

For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
same setting with host driver, or it will happen conflicts.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:16 -05:00
Shaoyun Liu
c5892230d9 drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine 
Change doorbell assignments to allow routing doorbells for 8 user
mode SDMA queues per engine.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:16 -05:00
Felix Kuehling
b62e01774b drm/amdgpu: remove unnecessary forward declaration 
struct vi_sdma_mqd is defined in vi_structs.h.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:15 -05:00
Jay Cornwall
5df099e8bc drm/amdkfd: Add wavefront context save state retrieval ioctl 
Wavefront context save data is of interest to userspace clients for
debugging static wavefront state. The MQD contains two parameters
required to parse the control stack and the control stack itself
is kept in the MQD from gfx9 onwards.

Add an ioctl to fetch the context save area and control stack offsets
and to copy the control stack to a userspace address if it is kept in
the MQD.

Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:15 -05:00
Felix Kuehling
5ade6c9c35 drm/amdkfd: Report SDMA firmware version in the topology 
Also save the version in struct kfd_dev so we only need to query
it once.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:14 -05:00
Harish Kasiviswanathan
13cd51a8f1 drm/amdgpu: Enable BAD_OPCODE intr for gfx8 
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in
response to bad opcodes in a CP queue.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:14 -05:00
Emily Deng
6d12aa8741 drm/amdkfd: KFD doesn't support TONGA SRIOV 
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV
environment, it will let compute ring IB test fail.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:14 -05:00
Eric Huang
d35f00d8ec drm/amdkfd: reflect atomic support in IO link properties 
Add the flags of properties according to Asic type and pcie
capabilities.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:13 -05:00
Andrey Grodzovsky
7bb086cd0b drm/amdgpu: Add warning message for INT SW fallback. 
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:13 -05:00
Andrey Grodzovsky
8c5e13ec6a Revert "drm/amdgpu: remove fence fallback" 
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55.
This commit breaks KCQ IB test and S3 on Polaris 11.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:13 -05:00
James Zhu
c95f75f4e8 drm/amdgpu:No action when VCN PG state is unchanged 
When VCN PG state is unchanged, it is unnecessary to reset power
gate state

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:12 -05:00