Despite CM_IDLEST1_CORE and CM_FCLKEN1_CORE behaving normal,
disabling SPI leads to messages like when suspending:
Powerdomain (core_pwrdm) didn't enter target state 0
and according to /sys/kernel/debug/pm_debug/count off state is not
entered. That was not connected to SPI during the discussion
of disabling SPI. See:
https://lore.kernel.org/linux-omap/20230122100852.32ae082c@aktux/
The reason is that SPI is per default in slave mode. Linux driver
will turn it to master per default. It slave mode, the powerdomain seems to
be kept active if active chip select input is sensed.
Fix that by explicitly disabling the SPI3 pins which used to be muxed by
the bootloader since they are available on an optionally fitted header
which would require dtb overlays anyways.
Fixes: a622310f7f ("ARM: dts: gta04: fix excess dma channel usage")
CC: stable@vger.kernel.org
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241204174152.2360431-1-andreas@kemnade.info
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
A bus_dma_limit was added for l3 bus by commit cfb5d65f25
("ARM: dts: dra7: Add bus_dma_limit for L3 bus") to fix an issue
observed only with SATA on DRA7-EVM with 4GB RAM and CONFIG_ARM_LPAE
enabled.
Since kernel 5.13, the SATA issue can be reproduced again following
the SATA node move from L3 bus to L4_cfg in commit 8af15365a3
("ARM: dts: Configure interconnect target module for dra7 sata").
Fix it by adding an empty dma-ranges property to l4_cfg and
segment@100000 nodes (parent device tree node of SATA controller) to
inherit the 2GB dma ranges limit from l3 bus node.
Note: A similar fix was applied for PCIe controller by commit
90d4d3f4ea ("ARM: dts: dra7: Fix bus_dma_limit for PCIe").
Fixes: 8af15365a3 ("ARM: dts: Configure interconnect target module for dra7 sata").
Link: https://lore.kernel.org/linux-omap/c583e1bb-f56b-4489-8012-ce742e85f233@smile.fr/
Cc: stable@vger.kernel.org # 5.13
Signed-off-by: Romain Naour <romain.naour@skf.com>
Link: https://lore.kernel.org/r/20241115102537.1330300-1-romain.naour@smile.fr
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Commit b9bf561261 ("ARM: dts: am335x-bone-common: Increase MDIO
reset deassert time") already increased the MDIO reset deassert delay
from 6.5 to 13 ms, but this may still cause Ethernet PHY probe failures:
SMSC LAN8710/LAN8720 4a101000.mdio:00: probe with driver SMSC LAN8710/LAN8720 failed with error -5
On BeagleBone Black Rev. C3, ETH_RESETn is controlled by an open-drain
AND gate. It is pulled high by a 10K resistor, and has a 4.7µF
capacitor to ground, giving an RC time constant of 47ms. As it takes
0.7RC to charge the capacitor above the threshold voltage of a CMOS
input (VDD/2), the delay should be at least 33ms. Considering the
typical tolerance of 20% on capacitors, 40ms would be safer. Add an
additional safety margin and settle for 50ms.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/9002a58daa1b2983f39815b748ee9d2f8dcc4829.1730366936.git.geert+renesas@glider.be
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Operating stable without reduced chip life at 1Ghz needs several
technologies working: The technologies involve
- SmartReflex
- DVFS
As this cannot directly specified in the OPP table as dependecies in the
devicetree yet, use the turbo flag again to mark this OPP as something
special to have some kind of opt-in.
So revert commit
5f1bf7ae84 ("ARM: dts: omap36xx: Remove turbo mode for 1GHz variants")
Practical reasoning:
At least the GTA04A5 (DM3730) has become unstable with that OPP enabled.
Furthermore nothing enforces the availability of said technologies,
even in the kernel configuration, so allow users to rather opt-in.
Cc: Stable@vger.kernel.org
Fixes: 5f1bf7ae84 ("ARM: dts: omap36xx: Remove turbo mode for 1GHz variants")
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20241018214727.275162-1-andreas@kemnade.info
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Pull SoC devicetree updates from Arnd Bergmann:
"New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the
last one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to many
new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both on the
consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very low
number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom and renesas
chips"
* tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (672 commits)
arm64: dts: allwinner: h5: NanoPi NEO Plus2: Use regulators for pio
arm64: dts: mediatek: add audio support for mt8365-evk
arm64: dts: mediatek: add afe support for mt8365 SoC
arm64: dts: mediatek: mt8186-corsola: Disable DPI display interface
arm64: dts: mediatek: mt8186: Add svs node
arm64: dts: mediatek: mt8186: Add power domain for DPI
arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*
arm64: dts: mt8183: add dpi node to mt8183
arm64: dts: allwinner: h5: NanoPi Neo Plus2: Fix regulators
arm64: dts: rockchip: add CAN0 and CAN1 interfaces to mecsbc board
arm64: dts: rockchip: add CAN-FD controller nodes to rk3568
arm64: dts: nuvoton: ma35d1: Add uart pinctrl settings
arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes
arm64: dts: nuvoton: Add syscon to the system-management node
ARM: dts: Fix undocumented LM75 compatible nodes
arm64: dts: toshiba: Fix pl011 and pl022 clocks
ARM: dts: stm32: Use SAI to generate bit and frame clock on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Switch bitclock/frame-master to flag on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Sort properties in audio endpoints on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Add MECIO1 and MECT1S board variants
...
"lm75" without any vendor is undocumented. It works with the Linux
kernel since the I2C subsystem will do matches of the compatible string
without a vendor prefix to the i2c_device_id and/or driver name.
Mostly replace "lm75" with "national,lm75" as that's the original part
vendor and the compatible which matches what "lm75" matched with. In a
couple of cases the node name or compatible gives a clue to the actual
part and vendor and a more specific compatible can be used. In these
cases, it does change the variant the kernel picks.
"nct75" is an OnSemi part which is compatible with TI TMP75C based on
a comparison of the OnSemi NCT75 datasheet and configuration the Linux
driver uses. Adding an OnSemi compatible would be an ABI change.
"nxp,lm75" is most likely an NXP part. Alexander Stein says the i.MX53
boards are a NXP LM75A as well. NXP makes a LM75A and LM75B. Both are
11-bit resolution and 100ms sample time. The "national,lm75a" is
9-bit, so "national,lm75b" is the closest match for both NXP variants.
While we're here, fix the node names to use the generic name
"temperature-sensor".
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com> # am335x-nano.dts
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx53-mba53.dts, imx53-tqma53.dtsi
Link: https://lore.kernel.org/r/20240816164717.1585629-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Prior to commit df16c1c51d ("net: phy: mdio_device: Reset device only
when necessary") MDIO reset deasserts were performed twice during boot.
Now that the second deassert is no longer performed, device probe
failures happen due to the change in timing with the following error
message:
SMSC LAN8710/LAN8720: probe of 4a101000.mdio:00 failed with error -5
Restore the original effective timing, which resolves the probe
failures.
Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
Link: https://lore.kernel.org/r/20240531183817.2698445-1-colin.foster@in-advantage.com
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
On dra76x, most dpll_gmac output clksel clocks are in registers from
CM_CLKSEL_DPLL_GMAC to CM_DIV_H13_DPLL_GMAC. In addition to that, there
are there more clocks in the CTRL_CORE_SMA_SW_0 register.
Let's group the CTRL_CORE_SMA_SW_0 clocks using the clksel binding to
reduce make W=1 dtbs unique_unit_address warnings, and stop using the
custom the ti,bit-shift property in favor of the standard reg property.
Let's also add a comment for the CTRL_CORE_SMA_SW_0 clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
The property ti,system-reboot-controller is no longer needed as the reboot
handler is now always registered. Remove this property.
While here remove the comment about delete-property, all K2G platforms use
PMMC, and it wasn't good advice anyway.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240326223730.54639-4-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The vendor kernel used 950mA as the default. The same value works fine on
the mainline Linux kernel, and has been tested extensively under Maemo
Leste [1] and postmarketOS, who have been using it for a number of years.
[1] fbc4ce7a84
Signed-off-by: Arthur Demchenkov <spinal.by@gmail.com>
Signed-off-by: Sicelo A. Mhlongo <absicsz@gmail.com>
Message-ID: <20240228083846.2401108-2-absicsz@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pull more ARM SoC updates from Arnd Bergmann:
"These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing"
* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
soc: fsl: dpio: fix kcalloc() argument order
bus: ts-nbus: Improve error reporting
bus: ts-nbus: Convert to atomic pwm API
riscv: dts: starfive: jh7110: Add camera subsystem nodes
ARM: bcm: stop selecing CONFIG_TICK_ONESHOT
ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
clk: ti: Improve clksel clock bit parsing for reg property
clk: ti: Handle possible address in the node name
dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
dt-bindings: riscv: cpus: reg matches hart ID
reset: Instantiate reset GPIO controller for shared reset-gpios
reset: gpio: Add GPIO-based reset controller
cpufreq: do not open-code of_phandle_args_equal()
of: Add of_phandle_args_equal() helper
reset: simple: add support for Sophgo SG2042
dt-bindings: reset: sophgo: support SG2042
riscv: dts: microchip: add specific compatible for mpfs pdma
riscv: dts: microchip: add missing CAN bus clocks
ARM: brcmstb: Add debug UART entry for 74165
...
Update TI clksel clocks to use reg
Updates for TI clksel clocks to use the standard reg property instead of
the non-standard ti,bit-shift legacy property.
There are still lots of TI composite clock related devicetree warnings for
missing bindings, and overlapping reg properties. We have grouped some of
the TI composite clocks under the clksel clock node, but did not consider
the reg property issue. Let's update the existing users before we continue
grouping more of the composite clocks.
* tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
clk: ti: Improve clksel clock bit parsing for reg property
clk: ti: Handle possible address in the node name
Link: https://lore.kernel.org/r/pull-1709102378-94138@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Devicetree changes for omaps for v6.9 merge window
Few device tree warning fixes, updates to use https links, and
add system-power-controller property for omap4-panda and
omap4-epson-embt2ws.
* tag 'omap-for-v6.9/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-panda-common: Enable powering off the device
ARM: dts: omap-embt2ws: system-power-controller for bt200
ARM: dts: omap: Switch over to https:// url
ARM: dts: ti: omap: add missing abb_{mpu,ivahd,dspeve,gpu} unit addresses for dra7 SoC
ARM: dts: ti: omap: add missing sys_32k_ck unit address for dra7 SoC
ARM: dts: ti: omap: add missing phy_gmii_sel unit address for dra7 SoC
Link: https://lore.kernel.org/r/pull-1709102762-376748@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
