Swap USART3 and UART8 aliases on STM32MP15xx DHCOM SoM,
make sure UART8 is listed first, USART3 second, because
the UART8 is labeled as UART2 on the SoM pinout, while
USART3 is labeled as UART3 on the SoM pinout.
Fixes: 34e0c7847d ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Enable the counter nodes without dedicated pins. With such configuration,
the counter interface can be used on internal clock to generate events.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Enable the counter nodes without dedicated pins. With such configuration,
the counter interface can be used on internal clock to generate events.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Enable the counter nodes without dedicated pins. With such configuration,
the counter interface can be used on internal clock to generate events.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This is a preparation patch in order to add lxa-tac generation 3
board.
As the gen3 board has a different adc and gpio{e,g} setups, move these
from the stm32mp15xc-lxa-tac.dtsi to the gen{1,2}.dts files.
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Some of the userspace software and tests depend on the can/i2c/spi
devices having the same name on every boot. This may not always be the
case based on e.g. parallel probe order.
Assign static device numbers to all can/i2c/spi devices.
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The RTC was enabled under the false assumption that the SoM already
contains a suitable 32.768 kHz crystal.
It does however not contain such a crystal and since none is fitted
externally to the SoM the RTC can not be used on the hardware.
Reflect that in the devicetree.
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The GIC IRQ type used for IPCC RX should be IRQ_TYPE_LEVEL_HIGH.
Replacing the interrupt with the EXTI event changes the type to
the numeric value 1, meaning IRQ_TYPE_EDGE_RISING.
The issue is that EXTI event 61 is a direct event.The IRQ type of
direct events is not used by EXTI and is propagated to the parent
IRQ controller of EXTI, the GIC.
Align the IRQ type to the value expected by the GIC by replacing
the second parameter "1" with IRQ_TYPE_LEVEL_HIGH.
Fixes: 7d9802bb0e ("ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151")
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Move the M24256E write-lockable page subnode after RTC subnode in
DH STM32MP13xx DHCOR SoM DT to keep the list of nodes sorted by I2C
address. No functional change.
Fixes: 3f2e7d1673 ("ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The STM32MP13xx DHCOR DHSBC is populated with STM32MP13xx part capable
of 1 GHz operation, increase the CPU core voltage to 1.35 V to make
sure the SoC is stable even if the blobs unconditionally force the CPU
to 1 GHz operation.
It is not possible to make use of CPUfreq on the STM32MP13xx because
the SCMI protocol 0x13 is not implemented by upstream OpTee-OS which
is the SCMI provider.
Fixes: 6331bddce6 ("ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Deduplicate /aliases { serialN = ... } and /chosen node into
stm32mp15xx-dhcom-som.dtsi , since the content is identical
on all carrier boards using the STM32MP15xx DHCOM SoM. No
functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
STM32 DT for v6.13, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- ST DK board:
- Add support of WLAN/BT Murata Type 1DX module.
- DH SOM:
- Add M24256E EEPROM suport.
- STMP32MP15:
- Use IWDG2 as wakeup source.
- Add support of WLAN/BT Murata Type 1DX module on DK2 board.
- STM32MP25:
- Enable RTC.
- Add DMA support for U(S)ART, I2C and SPI instances.
* tag 'stm32-dt-for-v6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
arm64: dts: st: add DMA support on SPI instances of stm32mp25
arm64: dts: st: add DMA support on I2C instances of stm32mp25
arm64: dts: st: add DMA support on U(S)ART instances of stm32mp25
arm64: dts: st: add RNG node on stm32mp251
arm64: dts: st: enable RTC on stm32mp257f-ev1 board
arm64: dts: st: add RTC on stm32mp25x
ARM: dts: stm32: add support of WLAN/BT on stm32mp135f-dk
ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2
ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp135f-dk
ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp157c-dk2
ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp13
ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15
ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT
ARM: dts: stm32: Add IWDG2 EXTI interrupt mapping and mark as wakeup source
Link: https://lore.kernel.org/r/92d2d6df-cc5c-488f-8ebd-550b1903db12@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On stm32mp135f-dk board, WLAN/BT module LPO_IN pin is wired to
RTC OUT2_RMP pin.
Provide a pinctrl configuration to enable LSCO on OUT2_RMP.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
On stm32mp157c-dk2 board, WLAN/BT module LPO_IN pin is wired to
RTC OUT2_RMP pin.
Provide a pinctrl configuration to enable LSCO on OUT2_RMP.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin
for RTC OUT2_RMP, in stm32mp13-pinctrl.dtsi.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin
for RTC OUT2_RMP, in stm32mp15-pinctrl.dtsi.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The STM32MP13xx DHCOR SoM is populated with M24256E EEPROM which has
Additional Write lockable page at separate I2C address. Describe the
page in DT to make it available.
Note that the WLP page on this device is hardware write-protected by
R37 which pulls the nWC signal high to VDD_3V3_1V8 power rail.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The IWDG2 is capable of generating pre-timeout interrupt, which can be used
to wake the system up from suspend to mem. Add the EXTI interrupt mapping
and mark the IWDG2 as wake up source.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
By default the SGTL5000 derives bit and frame clock from MCLK, which
does not produce particularly accurate results. The SGTL5000 PLL does
improve the accuracy, but also increases power consumption. Using the
SoC SAI interface as bit and frame clock source results in the best
accuracy without the power consumption increase downside. Switch the
bit and frame clock direction from SAI to SGTL5000, reduce mclk-fs to
match.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Switch the bitclock-master and frame-master properties from phandle to
flag on STM32MP15xx DHCOM PDK2. There is no real reason to use phandle
in this system DT, since the phandle points to the endpoint node which
contains the property itself. Simplify the DT. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Introduce device tree support for the MECIO1 and MECT1S board variants.
MECIO1 is an I/O and motor control board used in blood sample analysis
machines. MECT1S is a 1000Base-T1 switch for internal machine networks
of blood sample analysis machines.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Rename 'pins1' to 'pins' in the qspi_bk1_pins_a node to correct the
subnode name. The incorrect name caused the configuration to be
applied to the wrong subnode, resulting in QSPI not working properly.
Some additional changes was made:
- To avoid this kind of regression, all references to pin configuration
nodes are now referenced directly using the format &{label/subnode}.
- /delete-property/ bias-disable; was added everywhere where bias-pull-up
is used
- redundant properties like driver-push-pull are removed
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The RTL8211 PHY on DH STM32MP13xx DHCOR DHSBC carrier board supports HW
LED offload, the LEDs can be configured on link at 10/100/1000 line rate
and on RXTX activity. There are two PHYs on this board, each only has two
out of three LEDs connected to the PHY LED outputs. Describe this hardware
configuration in DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This enables DDR50 mode for the eMMC on Octavo OSD32MP1-RED board.
Fixes: be78ab4f63 ("ARM: dts: stm32: add initial support for stm32mp157-odyssey board")
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Describe ethernet MAC address nvmem cells in DH STM32MP13xx DHCOR DHSBC
board DT. The MAC address can be fused in BSEC OTP fuses and used to set
up MAC address for both ethernet MACs on this board.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The RTL8211F PHY clock output is not used on DH STM32MP13xx DHCOR DHSBC
board, disable it to improve EMI characteristics.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The RTL8211F PHY gets confused when the MDIO bus lines get switched
to ANALOG during suspend/resume cycle. Keep the MDIO and MDC lines
in AF during suspend/resume to avoid confusing the PHY. The PHY can
be brought out of the confused state by restarting auto-negotiation
too, but that seems like an odd workaround and shouldn't be in the
PHY driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
STM32 DT for v6.11, round 1
Highlights:
----------
-MCU:
- Add syscfg missing clock on stm32f429.
- MPU:
- STM32MP13:
- Add camera support on stm32mp135f-dk bord using DCMIPP and
GC2145 sensor.
- Document PWM output for stm32mp135f-dk
- Add goodix touchscreen support on stm32mp135f-dk board.
- Add new DH DHCOR / DHSBC board (Som + carrier board) based on
STM32MP135F SoC.
SOM part contains: STM32MP135F SoC, 512MB DDR2L RAM and
eMMC/SDIO wifi module.
The carrier boards embedds 2 RGMII ETH ports, USB-A,USB-C
and an extansion connector.
- Add Ethernet controller support on stm32mp135f-dk.
It uses LAN8742A PHY based on RMII.
- STMP32MP15:
- Rework Octavo OSD32MP1 split for USB phy.
- Add OP-TEE IRQ for asynchronous notification support.
It allows OP-TEE to trig Linux.
- STM32MP25:
- Add OP-TEE IRQ for asynchronous notification support.
It allows OP-TEE to trig Linux.
- Enable firewall for RCC.
- Add all U(s)ART nodes for stm32mp25.
- Add 3 power domains for low power modes.
- Add HPDMA support.
- Add Ethernet controller (ETH2) support on stm32mp257f-ev1.
It uses Realtek PHY based on RGMII.
- Add and enable SCMI regulator support.
* tag 'stm32-dt-for-v6.11-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (31 commits)
arm64: dts: st: describe power supplies for stm32mp257f-ev1 board
arm64: dts: st: add scmi regulators on stm32mp25
regulator: Add STM32MP25 regulator bindings
ARM: dts: stm32: omit unused pinctrl groups from stm32mp13 dtb files
arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 board
arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsi
arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25
arm64: dts: st: add HPDMA nodes on stm32mp251
ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board
ARM: dts: stm32: order stm32mp13-pinctrl nodes
ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
ARM: dts: stm32: Document output pins for PWMs on stm32mp135f-dk
ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards
ARM: dts: stm32: Missing clocks for stm32f429's syscfg.
ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
dt-bindings: arm: stm32: Add compatible string for DH electronics STM32MP13xx DHCOR DHSBC board
ARM: dts: stm32: osd32: move pwr_regulators to common
...
Link: https://lore.kernel.org/r/8f10bd29-d067-4060-89ff-2e1a605f3141@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
stm32mp13-pinctrl.dtsi contains nearly all pinctrl groups collected from
all boards. Most of them end up unused by a board and only waste binary
space. Add /omit-if-no-ref/ to the groups to scrub the unused groups
from the dtbs.
Use the following regex to update the file and drop two useless newlines too:
s@^\t[^:]\+: [^ ]\+ {$@\t/omit-if-no-ref/\r&@
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add ethernet support for the DH STM32MP13xx DHCOR DHSBC carrier board.
This carrier board is populated with two gigabit ethernet ports and two
Realtek RTL8211F PHYs, both are described in this DT patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Ethernet1: RMII with crystal
Ethernet2: RMII with no cristal, need "phy-supply" property to work,
today this property was managed by Ethernet glue, but should be present
and managed in PHY node. So I will push second Ethernet in next step.
PHYs used are SMSC (LAN8742A)
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board.
ethernet1: RMII with crystal.
ethernet2: RMII without crystal.
Add analog gpio pin configuration ("sleep") to manage power mode on
stm32mp13.
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
To simplify identifying the pins where the PWM output is routed to,
add a comment to each PWM device about the respective pin on the
expansion connector.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Without clock definition, SYSCFG will not work, EXTI interrupt for
port other than GPIOA will fail to operate.
Signed-off-by: Yanjun Yang <yangyj.ee@gmail.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
