Commit Graph

988 Commits

Author SHA1 Message Date
Kever Yang
abf55cdf9c dt-bindings: phy: rockchip,inno-usb2phy: add rk3562
Add compatible for the USB2 phy in the Rockchip RK3562 SoC.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 12:20:39 +01:00
Heiko Stuebner
d78b565371 dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible
Add compatible for the USB2 phy in the Rockchip RK3036 SoC.

Apart from some bits that got swapped around in the phy registers, the
block is nearly the same as the one on the rk3128.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 12:19:29 +01:00
Lad Prabhakar
9c4fbefc96 dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC.

RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it
needs additional configuration to be done as compared RZ/G2L USB2.0 phy.
To handle this difference a SoC specific compat string is added for
RZ/V2H(P) SoC.

Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets`
property and has two clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 12:14:59 +01:00
Lad Prabhakar
31eebeef8c dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family
The RZ/G2L family requires two clocks for USB2 PHY, which are already
defined in the DTSI files. Add a constraint in the DT binding document
to ensure validation with `dtbs_check`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 12:14:58 +01:00
Ivaylo Ivanov
e4c9a7b475 dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 support
Document support for Exynos2200. As the USBDRD 3.2 4nm controller
consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will
be handled by external drivers, define only the bus clocked used
by the link controller.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 11:43:37 +01:00
Ivaylo Ivanov
59cf754607 dt-bindings: phy: add exynos2200 eusb2 phy support
Document the exynos2200 eUSB2 compatible. Unlike the currently documented
Qualcomm SoCs, the driver doesn't make use of reset lines for reset
control and uses more clocks.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 11:43:37 +01:00
Rob Herring (Arm)
1d6fc048b8 dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schema
Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the
example to the GRF binding as that has the complete block.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 11:16:28 +01:00
Xu Yang
7325e0995f dt-bindings: phy: imx8mq-usb: add imx95 tuning support
The parameter value of below 3 properties are USB PHY specific. i.MX8MP
and i.MX95 USB PHY has different meanings. This will enlarge parameters
value and add constraints for them.

 - fsl,phy-tx-vref-tune-percent
 - fsl,phy-tx-rise-tune-percent
 - fsl,phy-comp-dis-tune-percent

Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 11:16:04 +01:00
Xu Yang
5b3a91b207 dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt property
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in
register PHY_CTRL3 bit[31:29].

  011: Corresponds to a launch amplitude of 1.12 V.
  010: Corresponds to a launch amplitude of 1.04 V.
  000: Corresponds to a launch amplitude of 0.88 V.

After updated:

  011: Corresponds to a launch amplitude of 0.844 V.
  100: Corresponds to a launch amplitude of 1.008 V.
  101: Corresponds to a launch amplitude of 1.156 V.

This will correct it accordingly.

Fixes: b2e75563dc ("dt-bindings: phy: imx8mq-usb: add phy tuning properties")
Cc: stable@vger.kernel.org
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 11:16:04 +01:00
AngeloGioacchino Del Regno
1b1e949924 dt-bindings: phy: mediatek,tphy: Add support for MT6893
Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC: this chip integrates a MediaTek generic T-PHY version 2.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:44:35 +01:00
AngeloGioacchino Del Regno
fe750a871d dt-bindings: phy: mediatek,dsi-phy: Add support for MT6893
Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI
PHY found in this chip is fully compatible with the one found in
the MT8183 SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:44:35 +01:00
Rob Herring (Arm)
2063eedf3c dt-bindings: phy: rockchip: Convert RK3399 Type-C PHY to schema
Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the
missing "power-domains" property and "port" and "orientation-switch"
properties in the child nodes.

Omit the previously deprecated properties as they aren't used anywhere.

Drop the 2nd example which was pretty much identical to the 1st example.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:32:02 +01:00
Siddharth Vadapalli
e00c9aea31 dt-bindings: phy: cadence-torrent: enable PHY_TYPE_USXGMII
The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the
bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value
of "12" while the existing maximum allowed PHY TYPE is "9", switch back to
using "enum" property in the bindings to account for this discontinuity.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:26:05 +01:00
Frank Wunderlich
b484b25a48 dt-bindings: phy: mtk-xs-phy: support type switch by pericfg
Add support for type switch by pericfg register between USB3/PCIe.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250422132438.15735-5-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:24:44 +01:00
Frank Wunderlich
117d09e283 dt-bindings: phy: mtk-xs-phy: Add mt7988 compatible
Add compatible for xs-phy on mt7988.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250422132438.15735-4-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14 09:24:43 +01:00
Nitheesh Sekar
aae29082b6 dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible
The IPQ5018 SoC contains a Gen2 1 and 2-lane PCIe UNIPHY which is the
same as the one found in IPQ5332. As such, add IPQ5018 compatible.

Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-1-e1828fef06c9@outlook.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-11 17:11:47 +05:30
Justin Chen
0fbceff4f8 dt-bindings: phy: brcmstb-usb-phy: Add support for bcm74110
bcm74110 brcmstb usb phy adds further power savings during suspend
states.

Signed-off-by: Justin Chen <justin.chen@broadcom.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250402185159.2976920-2-justin.chen@broadcom.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-11 12:51:12 +05:30
Kaustabh Chakraborty
23f793850e dt-bindings: phy: samsung,usb3-drd-phy: add exynos7870-usbdrd-phy compatible
Add the compatible string "samsung,exynos7870-usbdrd-phy" to the
documentation. The devicetree node requires two clocks, named "phy" and
"ref" (same as clocks required by Exynos5).

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250410-exynos7870-usbphy-v2-2-2eb005987455@disroot.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-10 19:12:16 +05:30
Rob Herring (Arm)
070d546258 dt-bindings: phy: rockchip: Add missing "phy-supply" property
Several Rockchip PHYs use the "phy-supply" property, but don't
document it. Add it to the current known users.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250407165607.2937088-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-10 18:47:54 +05:30
Kever Yang
86ae168934 dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible
rk3562 use the same Naneng Combo Phy driver as rk3568.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250227110836.2343158-1-kever.yang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-16 22:32:23 +05:30
Heiko Stuebner
301587cf4e dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema
Add dt-binding schema for the MIPI C-/D-PHY found on
Rockchip RK3588 SoCs.

Tested-by: Daniel Semkowicz <dse@thaumatec.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://lore.kernel.org/r/20250313134035.278133-2-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-16 22:10:46 +05:30
Ziyue Zhang
e46e59b77a dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2
Document the QMP PCIe PHY on the QCS8300 platform.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Link: https://lore.kernel.org/r/20250310063103.3924525-2-quic_ziyuzhan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11 12:25:52 +01:00
Nitin Rawat
12185bc38f dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY
Document the QMP UFS PHY on the SM8750 Platform.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Link: https://lore.kernel.org/r/20250310-sm8750_ufs_master-v2-1-0dfdd6823161@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11 12:24:46 +01:00
Nitheesh Sekar
a2e934885c dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250220094251.230936-2-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11 12:21:01 +01:00
Andre Przywara
1f7af7f3c3 dt-bindings: phy: document Allwinner A523 USB-2.0 PHY
The Allwinner A523 SoC contains a USB-2.0 PHY fully compatible to the
one used in the D1/T113s SoCs. This PHY controls the two USB-2.0 ports,
there is a separate and quite different PHY for the USB-3.0 port.

Add the new compatible string, with a fallback to the D1 version.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250307005712.16828-8-andre.przywara@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-10 12:44:27 +05:30
Sowon Na
0ee54dcfe7 dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings
Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20241226031142.1764652-2-sowon.na@samsung.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13 23:33:40 +05:30
André Draszik
c38528812c dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties
orientation-switch is the standard declaration to inform the Type-C mux
layer that a remote-endpoint is capable of processing orientation
change messages.

The USB PHY on gs101 needs to be configured based on the orientation of
the connector. For that the DTS needs a link between the phy's port and
a TCPCi, and we'll need to inform the phy driver that it should handle
the orientation (register a handler).

Update the schema to enforce that by requiring the orientation-switch
and port properties on gs101 (only). We disallow orientation-switch on
all other supported platforms, since other versions of this phy (or its
system integration) don't currently support or even need it.

Even though this new required gs101 property is an ABI break, the
intention for the driver is to behave as before if it's missing
(meaning for gs101 it will work in SS mode in one orientation only).
Other platforms are not affected.

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-2-f5961268b149@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13 22:42:52 +05:30
André Draszik
642b1ed4cd dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties
In [1], Rob pointed out that we should really be separating properties
with blank lines in between, which is universal style. Only where
properties are booleans, empty lines are not required.

Do so.

Link: https://lore.kernel.org/all/20240711212359.GA3023490-robh@kernel.org/ [1]
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-1-f5961268b149@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13 22:42:52 +05:30
Konrad Dybcio
f67f8c61b7 dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints
(Almost?) all QMP PHYs come with both a "full reset" ("phy") and a
"retain certain registers" one ("phy_nocsr").

Drop the maxItems=1 constraint for resets and reset_names as we go
ahead and straighten out the DT usage. After that's done (which
will involve modifying some clock drivers etc.), we may set
*min*Items to 2, bar some possible exceptions.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-2-72cd4cdc767b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10 22:38:55 +05:30
Konrad Dybcio
2e1ffd4c18 dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY
X1P42100 has two Gen4x4 PHYs instead of one Gen4x4 and one Gen4x8.

They are mostly identical to X1E80100's Gen4x4 PHY, but there are some
minor details in the programming sequences.

Introduce a new compatible for this flavor of the PHY.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-1-72cd4cdc767b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10 22:38:55 +05:30
Andy Yan
ad205ffc0d dt-bindings: phy: Add rk3576 hdptx phy
Add compatible for the HDPTX PHY on rk3576, which is compatible with
rk3588, but without rst_phy/rst_ropll/rst_lcpll.

In fact, these three reset lines are also optional on the rk3588,
they just used for debug, then they were removed on the rk3576 IC
design.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20241231092721.252405-1-andyshrk@163.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10 22:29:22 +05:30
Neil Armstrong
af1bc0ebe7 dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY
Document the two lanes PCIe PHY found on SM8350 SoCs along the
already documented single lane PCIe PHY.

This fixes:
/soc@0/phy@1c0e000: failed to match any schema with compatible: ['qcom,sm8350-qmp-gen3x2-pcie-phy']

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-topic-misc-sm8350-pcie-bindings-fix-v1-1-e8eaff1699d7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-25 01:17:33 +05:30
Manikanta Mylavarapu
74a5054ee9 dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs
Document the PCIe phy on the IPQ5424 platform using the
IPQ9574 bindings as a fallback, since the PCIe phy on the
IPQ5424 is similar to IPQ9574.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241213134950.234946-3-quic_mmanikan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-25 01:17:33 +05:30
Dmitry Baryshkov
5c4bfe3ee5 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible
Document compatible for the QMP PCIe PHY on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-2-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08 21:30:08 +05:30
Dmitry Baryshkov
d1cfda3b1e dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible
Document compatible for the USB+DP Combo PHY on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-1-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08 21:29:32 +05:30
Frank Wang
b136e9928d dt-bindings: phy: rockchip: add rk3576 compatible
Adds the compatible line to support RK3576 SoC.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241106021357.19782-1-frawang.cn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08 21:19:49 +05:30
Varadarajan Narayanan
d70656aee7 dt-bindings: phy: qcom,qmp-usb: Add IPQ5424 USB3 PHY
Add dt-bindings for USB3 PHY found on Qualcomm IPQ5424

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241118052839.382431-4-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04 19:59:29 +05:30
Varadarajan Narayanan
db4427afa6 dt-bindings: phy: qcom,qusb2: Document IPQ5424 compatible
Document the compatible string used for the qusb2 phy in IPQ5424.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241118052839.382431-2-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04 19:59:29 +05:30
Xu Yang
2318ca5994 dt-bindings: phy: imx8mq-usb: correct reference to usb-switch.yaml
The i.MX95 usb-phy can work with or without orientation-switch. With
current setting, if usb-phy works without orientation-switch, the
dt-schema check will show below error:

phy@4c1f0040: 'oneOf' conditional failed, one must be fixed:
        'port' is a required property
        'ports' is a required property
        from schema $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#

This will correct the behavior of referring to usb-switch.yaml.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241119105017.917833-1-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04 19:51:01 +05:30
Krishna chaitanya chundru
1e889f2bd8 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS615 QMP PCIe PHY Gen3 x1
Document the QMP PCIe PHY on the QCS615 platform.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241122023314.1616353-2-quic_ziyuzhan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04 19:11:17 +05:30
Linus Torvalds
e33a6d83e1 Merge tag 'usb-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
 "Here is the big set of USB and Thunderbolt changes for 6.13-rc1.

  Overall, a pretty slow development cycle, the majority of the work
  going into the debugfs interface for the thunderbolt (i.e. USB4) code,
  to help with debugging the myrad ways that hardware vendors get their
  interfaces messed up. Other than that, here's the highlights:

   - thunderbolt changes and additions to debugfs interfaces

   - lots of device tree updates for new and old hardware

   - UVC configfs gadget updates and new apis for features

   - xhci driver updates and fixes

   - dwc3 driver updates and fixes

   - typec driver updates and fixes

   - lots of other small updates and fixes, full details in the shortlog

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'usb-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (148 commits)
  usb: typec: tcpm: Add support for sink-bc12-completion-time-ms DT property
  dt-bindings: usb: maxim,max33359: add usage of sink bc12 time property
  dt-bindings: connector: Add time property for Sink BC12 detection completion
  usb: dwc3: gadget: Remove dwc3_request->needs_extra_trb
  usb: dwc3: gadget: Cleanup SG handling
  usb: dwc3: gadget: Fix looping of queued SG entries
  usb: dwc3: gadget: Fix checking for number of TRBs left
  usb: dwc3: ep0: Don't clear ep0 DWC3_EP_TRANSFER_STARTED
  Revert "usb: gadget: composite: fix OS descriptors w_value logic"
  usb: ehci-spear: fix call balance of sehci clk handling routines
  USB: make to_usb_device_driver() use container_of_const()
  USB: make to_usb_driver() use container_of_const()
  USB: properly lock dynamic id list when showing an id
  USB: make single lock for all usb dynamic id lists
  drivers/usb/storage: refactor min with min_t
  drivers/usb/serial: refactor min with min_t
  drivers/usb/musb: refactor min/max with min_t/max_t
  drivers/usb/mon: refactor min with min_t
  drivers/usb/misc: refactor min with min_t
  drivers/usb/host: refactor min/max with min_t/max_t
  ...
2024-11-29 11:19:31 -08:00
Linus Torvalds
0ce9a5ffca Merge tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
 "New hardware support:

   - ST STM32MP25 combophy support

   - Sparx5 support for lan969x serdes and updates to driver to support
     this

   - NXP PTN3222 eUSB2 to USB2 redriver

   - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2
     support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP
     UFS PHY support and SA8775P eDP PHY support

   - Rockchip rk3576 usbdp and rk3576 usb2 phy support

   - Binding for Microchip ATA6561 can phy

  Updates:

   - Freescale driver updates from hdmi support

   - Conversion of rockchip rk3228 hdmi phy binding to yaml

   - Broadcom usb2-phy deprecated support dropped and USB init array
     update for BCM4908

   - TI USXGMII mode support in J7200

   - Switch back to platform_driver::remove() subsystem update"

* tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits)
  phy: qcom: qmp: Fix lecacy-legacy typo
  phy: lan969x-serdes: add support for lan969x serdes driver
  dt-bindings: phy: sparx5: document lan969x
  phy: sparx5-serdes: add support for branching on chip type
  phy: sparx5-serdes: add indirection layer to register macros
  phy: sparx5-serdes: add function for getting the CMU index
  phy: sparx5-serdes: add ops to match data
  phy: sparx5-serdes: add constant for the number of CMU's
  phy: sparx5-serdes: add constants to match data
  phy: sparx5-serdes: add support for private match data
  phy: bcm-ns-usb2: drop support for old binding variant
  dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant
  dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300
  dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible
  dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561
  phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions
  phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll()
  phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l()
  phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out()
  phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL
  ...
2024-11-27 13:33:43 -08:00
Linus Torvalds
9c39d5ab45 Merge tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
 "This release adds the devicetree files for an impressive number of new
  SoC variants, though as expected these are all related to others we
  already support:

   - The microchip sam9x7 devicetree is now added, after the device
     driver and platform code has already made it in. This is likely the
     last ARMv5 (!) platform to ever get added, updating the 20+ year
     old at91/sam9 platform with DDR3 memory and gigabit ethernet.

   - On the Apple platform, there are now devicetree files for a number
     of A-series SoCs in addition to the M-series ones, these are used
     primarily in phones and tablets, but are closely related to the
     already supported chips.

   - Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in
     older Samsung Galaxy phones.

   - Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely
     related to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end
     laptops.

   - Rockchip RK3528 and RK3576 are new variants of their TV box and
     Tablet chips, still using the older ARMv8.0 cores from
     RK3328/RK3399 but with a newer process and other improvements from
     the RK35xx (otherwise ARMv8.2) chips. RK3566T and RK3399-S are also
     added, these are just lower-cost versions of their normal
     counterparts.

   - TI J742S2 is a feature-reduced version of the J784s4
     industrial/automotive SoC, with fewer CPU cores.

   - Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
     (Cortex-A53) core, at this point support is only added for running
     on the RISC-V side on the LicheeRV Nano board.

  A total of 92 new .dts files describing individual machines is added,
  which must be a new record. The majority of these is for the newly
  added chips above, notably all the Apple phones and tablets. The other
  new machines include nine industrial/embedded boards with NXP i.MX6 or
  i.MX8 SoCs, eight for Rockchips RK35XX and one or two each for
  Rockchips RV1109, RK3308, Allwinner A33, Tegra 234, Qualcomm
  qcs9100/sc8280xp/x1e80100, TI AM625 and Starfive JH7110.

  As usual there are also many newly added features in existing boards
  as well as cleanups and minor bugfixes"

* tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (718 commits)
  arm64: dts: apm: Remove unused and undocumented "bus_num" property
  arm: dts: spear13xx: Remove unused and undocumented "pl022,slave-tx-disable" property
  arm64: dts: amd: Remove unused and undocumented "amd,zlib-support" property
  arm64: dts: lg131x: Update spi clock properties
  arm64: dts: seattle: Update spi clock properties
  arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25
  arm64: dts: rockchip: add Radxa ROCK 5C
  dt-bindings: arm: rockchip: add Radxa ROCK 5C
  arm64: dts: rockchip: orangepi-5-plus: Enable GPU
  arm64: dts: rockchip: enable USB3 on NanoPC-T6
  arm64: dts: rockchip: adapt regulator nodenames to preferred form
  arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi GenBook
  arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi 4B
  arm64: dts: rockchip: Enable HDMI0 for rk3588 Cool Pi CM5 EVB
  arm64: dts: rockchip: Enable HDMI on NanoPi R6C/R6S
  arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
  arm64: dts: rockchip: Enable HDMI on Hardkernel ODROID-M2
  arm64: dts: rockchip: Remove non-removable flag from sdmmc on rk3576-sige5
  arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
  arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer
  ...
2024-11-20 15:26:46 -08:00
Greg Kroah-Hartman
85c4efbe60 Merge v6.12-rc6 into usb-next
We need the USB fixes in here as well, and this resolves a merge
conflict in:
	drivers/usb/typec/tcpm/tcpm.c

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Link: https://lore.kernel.org/r/20241101150730.090dc30f@canb.auug.org.au
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-11-05 09:56:08 +01:00
Cody Eksal
4402ef303d dt-bindings: phy: sun50i-a64: add a100 compatible
The USB PHY found in the A100 is similar to that found in the D1. Add a
compatible for the A100.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241031070232.1793078-4-masterr3c0rd@epochal.quest
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-11-02 19:32:39 +08:00
Daniel Machon
c569905547 dt-bindings: phy: sparx5: document lan969x
Lan969x is going to reuse the existing Sparx5 SERDES driver - document
that by adding compatible strings for the different SKU's that we
support, and a short description of the SERDES types and data rates
supported.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-8-d695bcb57b84@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-22 00:02:03 +05:30
Rafał Miłecki
c3639d423d dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant
The old binding variant (the one covering whole DMU block) was
deprecated 3 years ago. Linux kernel was warning when using it for
similar amount of time.

There aren't any known Northstar devices with bootloader providing DT to
operating system. Actually OpenWrt seems to be the only project using
this binding and it always appends DTB to kernel. It has switched to the
non-deprecated binding years ago.

Given there is close to zero chance this breaks anyone's setup it should
more than safe to drop this binding variant after 3 years.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240913044557.28315-1-zajec5@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 23:56:16 +05:30
Xin Liu
30c280bc8e dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300
Document the QMP UFS PHY compatible for Qualcomm QCS8300 to support
physical layer functionality for UFS found on the SoC. Use fallback to
indicate the compatibility of the QMP UFS PHY on the QCS8300 with that
on the SA8775P.

Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241018-qcs8300_ufs_phy_binding-v4-1-261c7c5fb8ff@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 23:46:18 +05:30
Dmitry Baryshkov
8e1e94619b dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible
Document the Synopsys eUSB2 PHY on the SAR2130P platform by using
the SM8550 as fallback.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-eusb2-v1-1-1cedd674ec64@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 23:37:50 +05:30
Abel Vesa
16fde3e076 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix X1E80100 resets entries
The PCIe 6a PHY is actually Gen4 4-lanes capable. So the gen4x4 compatible
describes it. But according to the schema, currently the gen4x4 compatible
doesn't require both PHY and PHY-nocsr resets, while the HW does. So fix
that by adding the gen4x4 compatible alongside the gen4x2 one for the
resets description.

Fixes: 0c5f4d23f7 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241021-phy-qcom-qmp-pcie-fix-x1e80100-gen4x4-resets-v3-1-1918c46fc37c@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21 23:33:25 +05:30