mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-02-19 11:21:15 -05:00
Code Issues Packages Projects Releases Wiki Activity
1,399,042 Commits 1 Branch 919 Tags
64ad6470c882fcaecfa4a1da96ea94de7ca0dc80
Commit Graph

877 Commits

Author SHA1 Message Date
Geert Uytterhoeven
b5788b96cb clk: renesas: r9a09g05[67]: Reduce differences 
The clock drivers for RZ/V2H and RZ/V2N are very similar.
Reduce the differences between them by:
  - Moving and reformatting the PLLCM33_GEAR clock definitions,
  - Replacing spaces by TABs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/2246d2263e8a24d1aaf653db2004cbf2263c9048.1757606097.git.geert+renesas@glider.be
 2025-09-12 09:53:37 +02:00
Biju Das
82e0aa95ec clk: renesas: r9a09g047: Add USB3.0 clocks/resets 
Add USB3.0 clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250909180803.140939-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-12 09:53:37 +02:00
Yuan CHen
cc55fc58fc clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init() 
In case of krealloc_array() failure, the current error handling just
returns from the function without freeing the original array.
Fix this memory leak by freeing the original array.

Fixes: 6aa1754764 ("clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system")
Signed-off-by: Yuan CHen <chenyuan@kylinos.cn>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250908012810.4767-1-chenyuan_fl@163.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-12 09:52:47 +02:00
Lad Prabhakar
2cfff084f0 clk: renesas: r9a09g056: Add clock and reset entries for I3C 
Add module clock entries for the I3C controller on the RZ/V2N
(R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250904155507.245744-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-11 20:23:15 +02:00
Lad Prabhakar
23c59916ba clk: renesas: r9a09g057: Add clock and reset entries for I3C 
Add module clock entries for the I3C controller on the RZ/V2H(P)
(R9A09G057) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250904155507.245744-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-11 20:23:15 +02:00
Lad Prabhakar
09e3a04673 clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks 
Add module and core clocks used by Ethernet Subsystem (Ethernet_SS),
Ethernet MAC (GMAC), Ethernet Switch (ETHSW).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250904071954.3176806-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-04 11:33:10 +02:00
Tommaso Merciai
08eea73dcf clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert() 
Replace the ternary operator with a direct boolean comparison to improve
code readability and maintainability. The logic remains unchanged.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250903082757.115778-5-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-04 11:30:01 +02:00
Tommaso Merciai
f8c002165c clk: renesas: rzv2h: Re-assert reset on deassert timeout 
Prevent issues during reset deassertion by re-asserting the reset if a
timeout occurs when trying to deassert. This ensures the reset line is in a
known state and improves reliability for hardware that may not immediately
clear the reset monitor bit.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/20250903082757.115778-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-04 11:29:32 +02:00
Tommaso Merciai
f8c5f0dc77 clk: renesas: rzg2l: Re-assert reset on deassert timeout 
Prevent issues during reset deassertion by re-asserting the reset if a
timeout occurs when trying to deassert. This ensures the reset line is in a
known state and improves reliability for hardware that may not immediately
clear the reset monitor bit.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/20250903082757.115778-3-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-04 11:29:31 +02:00
Tommaso Merciai
341b0f1b6c clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert() 
Combine common code from rzg2l_cpg_assert() and rzg2l_cpg_deassert() into a
new __rzg2l_cpg_assert() helper to avoid code duplication. This reduces
maintenance effort and improves code clarity.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/20250903082757.115778-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-04 11:29:31 +02:00
Biju Das
6bbf77bb22 clk: renesas: r9a09g047: Add GPT clocks and resets 
Add clock and reset entries for the Renesas RZ/G3E GPT{0,1} IPs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250820103053.93382-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-25 15:57:49 +02:00
Lad Prabhakar
07e7ccd804 clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5 
Add asynchronous core clocks and module clocks for SCI channels 1
through 5 on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812171720.3245851-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:32 +02:00
Brian Masney
54653bb3ec clk: renesas: rzv2h: remove round_rate() in favor of determine_rate() 
This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250811-clk-for-stephen-round-rate-v1-93-b3bf97b038dc@redhat.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:32 +02:00
Brian Masney
58afc20783 clk: renesas: rzg2l: convert from round_rate() to determine_rate() 
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250811-clk-for-stephen-round-rate-v1-92-b3bf97b038dc@redhat.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:32 +02:00
Claudiu Beznea
8933612860 clk: renesas: r9a07g04[34]: Use tabs instead of spaces 
Use tabs instead of spaces in the CRU clock descriptions to match the
formatting used in the rest of the clock definitions.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:32 +02:00
Claudiu Beznea
0f078d37ae clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL 
Add MSTOP configuration for all the module clocks on the RZ/G2UL
based SoCs (RZ/G2UL, RZ/Five).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:32 +02:00
Claudiu Beznea
56de5e305d clk: renesas: r9a07g044: Add MSTOP for RZ/G2L 
Add MSTOP configuration for all the module clocks on the RZ/G2L
based SoCs (RZ/G2L, RZ/G2LC, RZ/V2L).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:32 +02:00
Claudiu Beznea
f0cb3463d0 clk: renesas: r9a08g045: Add MSTOP for GPIO 
The GPIO module also supports MSTOP. Add it in the description of the gpio
clock.

Fixes: c496959527 ("clk: renesas: r9a08g045: Drop power domain instantiation")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:31 +02:00
Lad Prabhakar
45bf4bff28 clk: renesas: r9a09g077: Add USB core and module clocks 
Add module and core clocks used by USB.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250804202643.3967484-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:16:31 +02:00
Tommaso Merciai
059db30b32 clk: renesas: r9a09g047: Add DMAC clocks and resets 
Add clock and reset entries for the Renesas RZ/G3E DMAC IPs.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250801084825.471011-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:15:41 +02:00
Claudiu Beznea
6b234eda88 clk: renesas: r9a08g045: Add PCIe clocks and resets 
Add clocks and resets for the PCIe IP available on the Renesas RZ/G3S
SoC.  The clkl1pm clock is required for PCIe link power management (PM)
control and should be enabled based on the state of the CLKREQ# pin.
Therefore, mark it as a no_pm clock to allow the PCIe driver to manage
it during link PM transitions.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250704161410.3931884-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:15:41 +02:00
Wolfram Sang
148bda0cfe clk: renesas: r9a08g045: Add I3C clocks and resets 
Extracted from the BSP driver and rebased.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250630192438.38311-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-20 09:15:41 +02:00
Geert Uytterhoeven
f63aaf6e71 clk: renesas: mstp: Add genpd OF provider at postcore_initcall() 
Genpd OF providers must now be registered after genpd bus registration.
However, cpg_mstp_add_clk_domain() is only called from CLK_OF_DECLARE(),
which is too early.  Hence on R-Car M1A, R-Car H1, and RZ/A1, the
CPG/MSTP Clock Domain fails to register, and any devices residing in
that clock domain fail to probe.

Fix this by splitting initialization into two steps:
  - The first part keeps on registering the PM domain with genpd at
    CLK_OF_DECLARE(),
  - The second and new part moves the registration of the genpd OF
    provider to a postcore_initcall().

See also commit c5ae5a0c61 ("pmdomain: renesas: rcar-sysc: Add
genpd OF provider at postcore_initcall").

Fixes: 18a3a510ec ("pmdomain: core: Add the genpd->dev to the genpd provider bus")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/81ef5f8d5d31374b7852b05453c52d2f735062a2.1755073087.git.geert+renesas@glider.be
 2025-08-18 09:36:55 +02:00
Claudiu Beznea
0ab2d84f94 clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well 
If MSTOP is not added for both clocks in a coupled pair, and the clocks
are not disabled in the reverse order of their enable sequence, the MSTOP
may remain enabled when disabling the clocks.

This happens because rzg2l_mod_clock_endisable() executes for coupled
clocks only when a single clock from the pair is enabled. If one clock has
no MSTOP defined, it can result in the MSTOP configuration being left
active when the clocks are disabled out of order (i.e., not in the reverse
order of enabling).

Fixes: c496959527 ("clk: renesas: r9a08g045: Drop power domain instantiation")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250704134328.3614317-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-08 11:36:16 +02:00
John Madieu
e6e54229f3 clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs 
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250702005706.1200059-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-08 11:36:16 +02:00
Lad Prabhakar
fc7dd51537 clk: renesas: r9a09g057: Add XSPI clock/reset 
Add clock and reset entries for the XSPI interface on the R9A09G057 SoC.

While at it, rename CLK_PLLCM33_DIV4_PLLCM33 to CLK_PLLCM33_GEAR to align
with the terminology used in the hardware manual.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:53:35 +02:00
Lad Prabhakar
20e31205ae clk: renesas: r9a09g056: Add XSPI clock/reset 
Add XSPI clock and reset entries.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:53:35 +02:00
Lad Prabhakar
87239caea4 clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting 
Add support for fixed-factor module clocks that can report their enable
status through the module status monitor. Introduce a new clock type,
CLK_TYPE_FF_MOD_STATUS, and define the associated structure,
rzv2h_ff_mod_status_clk, to manage these clocks.

Implement the .is_enabled callback by reading the module status register
using monitor index and bit definitions. Provide a helper macro,
DEF_FIXED_MOD_STATUS, to simplify the definition of such clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:53:35 +02:00
Lad Prabhakar
7aada0abe9 clk: renesas: r9a09g057: Add support for xspi mux and divider 
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and
pllcm33_xspi divider to select different clock rates. Add support for
both.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:53:35 +02:00
Lad Prabhakar
2a4c0e785a clk: renesas: r9a09g056: Add support for xspi mux and divider 
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and
pllcm33_xspi divider to select different clock rates. Add support for
both.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:53:35 +02:00
Lad Prabhakar
0475a478d0 clk: renesas: r9a09g077: Add RIIC module clocks 
Add RIIC module clocks for: iic0, iic1, and iic2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:51:46 +02:00
Lad Prabhakar
09d50e09fa clk: renesas: r9a09g077: Add PLL2 and SDHI clock support 
Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
operating at 800MHz.

Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
clock source.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:51:43 +02:00
Lad Prabhakar
8250a8a9b1 clk: renesas: rzv2h: Drop redundant base pointer from pll_clk 
The base address can be accessed via the priv pointer already present in
struct pll_clk, making the separate base field redundant. Remove the base
member and its assignment.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624153049.462535-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:38:06 +02:00
Fabrizio Castro
6132643bfd clk: renesas: r9a09g057: Add entries for the RSPIs 
Add clock and reset entries for the Renesas RZ/V2H(P) RSPI IPs.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624192304.338979-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-07-02 20:36:51 +02:00
Fabrizio Castro
b7c26cbd5b clk: renesas: rzv2h: Add missing include file 
File `rzv2h-cpg.h' makes use of data types defined in `linux/types.h',
but it does not include the latter, which could lead to build errors.

Include `linux/types.h' to fix this problem.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624192748.340196-1-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-26 16:28:50 +02:00
Raag Jadav
338b505d56 clk: renesas: rzv2h: Use devm_kmemdup_array() 
Convert to use devm_kmemdup_array() which is more robust.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250610072809.1808464-1-raag.jadav@intel.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-24 10:00:35 +02:00
Lad Prabhakar
8b8ca27975 clk: renesas: Add CPG/MSSR support to RZ/N2H SoC 
Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing
the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs
share the same clock and reset architecture.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-19 20:19:19 +02:00
Lad Prabhakar
275e2b544d clk: renesas: r9a09g077: Add PCLKL core clock 
Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077)
SoC.  PCLKL is sourced from PLL1 and runs at 62.5MHz.  It is used by
various low-speed peripherals such as IIC and WDT.

Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring
correct enumeration of core clocks exposed to DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-19 20:19:05 +02:00
Tommaso Merciai
c939b63f44 clk: renesas: r9a09g047: Add I3C0 clocks and resets 
Add I3C0 clock and reset support to the Renesas RZ/G3E R9A09G047 CPG
driver.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250611093934.4208-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-19 19:56:15 +02:00
Lad Prabhakar
715676d841 clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocks 
Commit bc4d25fdfa ("clk: renesas: rzv2h: Add support for dynamic
switching divider clocks") missed setting the `CLK_SET_RATE_PARENT`
flag when registering ddiv clocks.

Without this flag, rate changes to the divider clock do not propagate
to its parent, potentially resulting in incorrect clock configurations.

Fix this by setting `CLK_SET_RATE_PARENT` in the clock init data.

Fixes: bc4d25fdfa ("clk: renesas: rzv2h: Add support for dynamic switching divider clocks")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609140341.235919-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-13 11:22:52 +02:00
Geert Uytterhoeven
b263e653c3 clk: renesas: rzg2l: Rename mstp_clock to mod_clock 
The mstp_clock structure really represents a module clock (cfr. the
various rzg2l_mod_clock_*() functions and the to_mod_clock() helper),
and is not directly related to the "Module stop state".
Rename it to "mod_clock", and replace "mstp_clock" by "mod_clock".
to avoid confusion with the mstop registers.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/53b3a730a784650762cdb27fdbde7a45b0c20db8.1749119264.git.geert+renesas@glider.be
 2025-06-10 10:32:39 +02:00
Lad Prabhakar
e6b6e3e08f clk: renesas: r9a09g056: Add clock and reset entries for USB2.0 
Add clock and reset entries for USB2.0.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250528132558.167178-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:32:35 +02:00
Claudiu Beznea
26a301a244 clk: renesas: rzg2l: Drop MSTOP based power domain support 
Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain core code.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-7-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:24:17 +02:00
Claudiu Beznea
c496959527 clk: renesas: r9a08g045: Drop power domain instantiation 
Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain instantiations.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:24:17 +02:00
Claudiu Beznea
5cd33db569 clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API 
The RZ/{G2L,V2L,G3S} CPG versions support a feature called MSTOP.  Each
module has one or more MSTOP bits associated with it, and these bits
need to be configured along with the module clocks. Setting the MSTOP
bits switches the module between normal and standby states.

Previously, MSTOP support was abstracted through power domains (struct
generic_pm_domain::{power_on, power_off} APIs).  With this abstraction,
the order of setting the MSTOP and CLKON bits was as follows:

Previous Order:
A/ Switching to Normal State (e.g., during probe):
1/ Clear module MSTOP bit
2/ Set module CLKON bit

B/ Switching to Standby State (e.g., during remove):
1/ Clear CLKON bit
2/ Set MSTOP bit

However, in some cases (when the clock is disabled through devres), the
order may have been (due to the issue described in link section):

1/ Set MSTOP bit
2/ Clear CLKON bit

Recently, the hardware team has suggested that the correct order to set
the MSTOP and CLKON bits is:

Updated Order:
A/ Switching to Normal State (e.g., during probe):
1/ Set CLKON bit
2/ Clear MSTOP bit

B/ Switching to Standby State (e.g., during remove):
1/ Set MSTOP bit
2/ Clear CLKON bit

To prevent future issues due to incorrect ordering, the MSTOP setup has
now been implemented in rzg2l_mod_clock_endisable(), ensuring compliance
with the sequence suggested in Figure 41.5: Module Standby Mode
Procedure from the RZ/G3S HW manual, Rev1.10.

Additionally, since multiple clocks of a single module may be mapped to
a single MSTOP bit, MSTOP setup is reference-counted.

Furthermore, as all modules start in the normal state after reset, if
the module clocks are disabled, the module state is switched to standby.
This prevents keeping the module in an invalid state, as recommended by
the hardware team.

Link: https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@bp.renesas.com/
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250527112403.1254122-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:24:17 +02:00
Claudiu Beznea
3fd4a8bb4b clk: renesas: rzg2l: Add macro to loop through module clocks 
Add a macro to iterate over the module clocks array. This will be useful
in the upcoming commits that move MSTOP support into the clock
enable/disable APIs.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:24:17 +02:00
Thierry Bultel
065fe720ee clk: renesas: Add support for R9A09G077 SoC 
RZ/T2H has 2 register blocks at different addresses.

The clock tree has configurable dividers and mux selectors.
Add these new clock types, new register layout type, and
registration code for mux and div in registration callback.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515141828.43444-6-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:24:17 +02:00
Thierry Bultel
3d37ca1482 clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 
In a subsequent patch, the registration callback will need more parameters
from cpg_mssr_priv (like another base address with clock controllers
with double register block, and also, notifiers and rmw_lock).
Instead of adding more parameters, move the needed parameters to a public
sub-struct.
Instead moving clks to this structure, which would have implied to add
an allocation (and cleanup) for it, keep the way the allocation is done
and just have a copy of the pointer in the public structure.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Link: https://lore.kernel.org/20250515141828.43444-5-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:20:45 +02:00
Claudiu Beznea
a68ea80f85 clk: renesas: rzg2l: Move pointers after hw member 
Reorder the pointer members in struct mstp_clock so they appear immediately
after the hw member. This helps avoid potential padding and eliminates the
need for any calculations in the to_mod_clock() macro. As struct clk_hw
currently contains only pointers, placing it first also avoids padding.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250514090415.4098534-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:20:45 +02:00
Claudiu Beznea
2f96afdffa clk: renesas: rzg2l: Postpone updating priv->clks[] 
Since the sibling data is filled after the priv->clks[] array entry is
populated, the first clock that is probed and has a sibling will
temporarily behave as its own sibling until its actual sibling is
populated. To avoid any issues, postpone updating priv->clks[] until after
the sibling is populated.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250514090415.4098534-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-06-10 10:20:45 +02:00