Pull SoC update from Arnd Bergmann:
"Convert ep93xx to devicetree
This concludes a long journey towards replacing the old board files
with devictree description on the Cirrus Logic EP93xx platform.
Nikita Shubin has been working on this for a long time, for details
see the last post on
https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/"
* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples
MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer
soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config
net: cirrus: use u8 for addr to calm down sparse
dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0
dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe()
pinctrl: ep93xx: Fix raster pins typo
spi: ep93xx: update kerneldoc comments for ep93xx_spi
clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()
clk: ep93xx: add module license
dmaengine: cirrus: remove platform code
ASoC: cirrus: edb93xx: Delete driver
ARM: ep93xx: soc: drop defines
ARM: ep93xx: delete all boardfiles
ata: pata_ep93xx: remove legacy pinctrl use
pwm: ep93xx: drop legacy pinctrl
ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
ARM: dts: ep93xx: Add EDB9302 DT
ARM: dts: ep93xx: add ts7250 board
ARM: dts: add Cirrus EP93XX SoC .dtsi
...
Pull pin control updates from Linus Walleij:
"Core changes:
- Add support for "input-schmitt-microvolt" property, as used in the
Sophgo SoC
New drivers:
- Mobileye EyeQ5 pin controller, I think this is an automotive SoC
- Rockchip rk3576 pin control support
- Sophgo CV1800 series pin controllers: CV1800B, CV1812H and SG2000
Improvements:
- Gradual improvements to Renesas, Samsung, Qualcomm, Nuvoton and a
few other drivers"
* tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (67 commits)
pinctrl: intel: Constify struct intel_pinctrl parameter
pinctrl: Remove redundant null pointer checks in pinctrl_remove_device_debugfs()
pinctrl: baytrail: Drop duplicate return statement
pinctrl: intel: Inline intel_gpio_community_irq_handler()
dt-bindings: pinctrl: qcom: add missing type to GPIO hogs
pinctrl: madera: Simplify with dev_err_probe()
pinctrl: k210: Use devm_clk_get_enabled() helpers
pinctrl: Join split messages and remove double whitespace
pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases
pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration
pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API
pinctrl: mvebu: Fix devinit_dove_pinctrl_probe function
pinctrl: sunxi: Use devm_clk_get_enabled() helpers
pinctrl: sophgo: cv18xx: fix missed __iomem type identifier
pinctrl: stmfx: Use string_choices API instead of ternary operator
pinctrl: nomadik: Use kmemdup_array instead of kmemdup for multiple allocation
pinctrl: intel: Introduce for_each_intel_gpio_group() helper et al.
pinctrl: intel: Constify intel_get_community() returned object
pinctrl: intel: Implement high impedance support
pinctrl: intel: Add __intel_gpio_get_direction() helper
...
The size of the mux stride was off by one, which could result in
invalid pin configuration on the device side or invalid state
readings on the software side.
While on it also update the code and:
- Increase the mux stride size to 16
- Align the virtual muxed regmap range to 16
- Start the regmap window at the selector
- Mark reserved registers as not-readable
Fixes: 8670de9fae ("pinctrl: cy8c95x0: Use regmap ranges")
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reported-by: Andy Shevchenko <andy@kernel.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/20240902072859.583490-1-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
intel-pinctrl for v6.11-1
This includes a new ACPI ID that is added to the Intel Meteor Lake
driver to support recent Intel Arrow Lake hardware.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
intel-pinctrl for v6.12-1
* Enable High Impedance pin configuration support for Intel pin control
* Miscellaneous small improvements here and there
The following is an automated git shortlog grouped by driver:
baytrail:
- Drop duplicate return statement
intel:
- Constify struct intel_pinctrl parameter
- Inline intel_gpio_community_irq_handler()
- Introduce for_each_intel_gpio_group() helper et al.
- Constify intel_get_community() returned object
- Implement high impedance support
- Add __intel_gpio_get_direction() helper
- Refactor __intel_gpio_set_direction() to be more useful
- Move debounce validation out of the lock
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are a few functions that do not and should not change
the state of the pin control object. Constify the respective
parameter.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Since we have for_each_intel_pad_group() helper, there is
no advantage of having intel_gpio_community_irq_handler().
Inline it into intel_gpio_irq().
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
On X1E80100, GPIO interrupts for wakeup-capable pins have been broken since
the introduction of the pinctrl driver. This prevents keyboard and touchpad
from working on most of the X1E laptops. So far we have worked around this
by manually building a kernel with the "wakeup-parent" removed from the
pinctrl node in the device tree, but we cannot expect all users to do that.
Implement a similar workaround in the driver by clearing the wakeirq_map
for X1E80100. This avoids using the PDC wakeup parent for all GPIOs
and handles the interrupts directly in the pinctrl driver instead.
The PDC driver needs additional changes to support X1E80100 properly.
Adding a workaround separately first allows to land the necessary PDC
changes through the normal release cycle, while still solving the more
critical problem with keyboard and touchpad on the current stable kernel
versions. Bypassing the PDC is enough for now, because we have not yet
enabled the deep idle states where using the PDC becomes necessary.
Cc: stable@vger.kernel.org
Fixes: 05e4941d97 ("pinctrl: qcom: Add X1E80100 pinctrl driver")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/20240830-x1e80100-bypass-pdc-v1-1-d4c00be0c3e3@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Switch to use dev_err_probe() to simplify the error path and
unify a message template.
Using this helper is totally fine even if err is known to never
be -EPROBE_DEFER.
The benefit compared to a normal dev_err() is the standardized format
of the error code, it being emitted symbolically and the fact that
the error code is returned which allows more compact error paths.
Signed-off-by: Yan Zhen <yanzhen@vivo.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/20240829044835.2047794-1-yanzhen@vivo.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Support for enabling the digital noise filter, and support for
configuring the noise filter stages (via the FILNUM register) and the
sampling interval (via the FILCLKSEL register) are related: a pin
supports either all or none of them. Hence simplify declaring digital
noise filter support for a pin by using a single feature flag instead of
three separate flags.
This patch removes the PIN_CFG_FILNUM and PIN_CFG_FILCLKSEL configuration
macros and renames PIN_CFG_FILONOFF to PIN_CFG_NF.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240829194841.84398-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Introduce a helper macro for_each_intel_gpio_group() et al.
With those in place, update the users.
It reduces the C code base as well as shrinks the binary:
add/remove: 0/0 grow/shrink: 4/21 up/down: 39/-621 (-582)
Total: Before=15942, After=15360, chg -3.65%
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Add __intel_gpio_get_direction() helper which provides all possible
physical states of the pad.
With that done, update current users and make the respective checks
consistent.
While at it, make the style of anonymous enum kernel documentation
consistent.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Refactor __intel_gpio_set_direction() to be more useful, i.e.
1) use one parameter per each direction to support all combinatios;
2) move IO to the only user that needs it.
With that done, update current users and deduplicate existing code.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
There is no need to validate debounce value under the lock.
Move it outside.
It also results in a smaller binary:
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-11 (-11)
Total: Before=15374, After=15363, chg -0.07%
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Samsung pinctrl drivers changes for v6.12
1. Few cleanups: use more appropriate of_property_present(), use scoped
OF nodes handling and switch to kmemdup_array().
2. Implement configuring pull-up and pull-down via GPIOLIB.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: renesas: Updates for v6.12
- Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC,
- Miscellaneous fixes and improvements.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The base iomux offsets for each GPIO pin line are accumulatively
calculated based off iomux width flag in rockchip_pinctrl_get_soc_data.
If the iomux width flag is one of IOMUX_WIDTH_4BIT, IOMUX_WIDTH_3BIT or
IOMUX_WIDTH_2BIT, the base offset for next pin line would increase by 8
bytes, otherwise it would increase by 4 bytes.
Despite most of GPIO2-B iomux have 2-bit data width, which can be fit
into 4 bytes space with write mask, it actually take 8 bytes width for
whole GPIO2-B line.
Commit e8448a6c81 ("pinctrl: rockchip: fix pinmux bits for RK3328
GPIO2-B pins") wrongly set iomux width flag to 0, causing all base
iomux offset for line after GPIO2-B to be calculated wrong. Fix the
iomux width flag to IOMUX_WIDTH_2BIT so the offset after GPIO2-B is
correctly increased by 8, matching the actual width of GPIO2-B iomux.
Fixes: e8448a6c81 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
Cc: stable@vger.kernel.org
Reported-by: Richard Kojedzinszky <richard@kojedz.in>
Closes: https://lore.kernel.org/linux-rockchip/4f29b743202397d60edfb3c725537415@kojedz.in/
Tested-by: Richard Kojedzinszky <richard@kojedz.in>
Signed-off-by: Huang-Huang Bao <i@eh5.me>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Trevor Woerner <twoerner@gmail.com>
Link: https://lore.kernel.org/20240709105428.1176375-1-i@eh5.me
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Replace SET_LATE_SYSTEM_SLEEP_PM_OPS() with its modern
LATE_SYSTEM_SLEEP_PM_OPS() alternative.
The combined usage of pm_sleep_ptr() and LATE_SYSTEM_SLEEP_PM_OPS() allows
the compiler to evaluate if the runtime suspend/resume() functions
are used at build time or are simply dead code.
This allows removing the __maybe_unused notation from the runtime
suspend/resume() functions.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/20240808162750.244092-1-festevam@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Despite its name, commit fed74d7527 ("pinctrl: mediatek: common-v2:
Fix bias-disable for PULL_PU_PD_RSEL_TYPE") actually broke bias-disable
for PULL_PU_PD_RSEL_TYPE.
mtk_pinconf_bias_set_combo() tries every bias method supported by the
pin until one succeeds. For PULL_PU_PD_RSEL_TYPE pins, before the
breaking commit, mtk_pinconf_bias_set_rsel() would be called first to
try and set the RSEL value (as well as PU and PD), and if that failed,
the only other valid option was that bias-disable was specified, which
would then be handled by calling mtk_pinconf_bias_set_pu_pd() and
disabling both PU and PD.
The breaking commit misunderstood this logic and added an early "return
0" in mtk_pinconf_bias_set_rsel(). The result was that in the
bias-disable case, the bias was left unchanged, since by returning
success, mtk_pinconf_bias_set_combo() no longer tried calling
mtk_pinconf_bias_set_pu_pd() to disable the bias.
Since the logic for configuring bias-disable on PULL_PU_PD_RSEL_TYPE
pins required mtk_pinconf_bias_set_rsel() to fail first, in that case,
an error was printed to the log, eg:
mt8195-pinctrl 10005000.pinctrl: Not support rsel value 0 Ohm for pin = 29 (GPIO29)
This is what the breaking commit actually got rid of, and likely part of
the reason why that commit was thought to be fixing functionality, while
in reality it was breaking it.
Instead of simply reverting that commit, restore the functionality but
in a way that avoids the error from being printed and makes the code
less confusing:
* Return 0 explicitly if a bias method was successful
* Introduce an extra function mtk_pinconf_bias_set_pu_pd_rsel() that
calls both mtk_pinconf_bias_set_rsel() (only if needed) and
mtk_pinconf_bias_set_pu_pd()
* And analogously for the corresponding getters
Fixes: fed74d7527 ("pinctrl: mediatek: common-v2: Fix bias-disable for PULL_PU_PD_RSEL_TYPE")
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/20240808-mtk-rsel-bias-disable-fix-v1-1-1b4e85bf596c@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
