Commit Graph

368847 Commits

Author SHA1 Message Date
Julia Lawall
a9856ef759 pinctrl: ti-iodelay: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops and pctlops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:42:48 +02:00
Julia Lawall
eb190c3402 pinctrl: tz1090: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:42:19 +02:00
Julia Lawall
78094f19e1 pinctrl: tz1090-pdc: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:42:00 +02:00
Julia Lawall
39a303674f pinctrl: tb10x: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:41:40 +02:00
Julia Lawall
b82bfae143 pinctrl: rza1: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinmux_ops structure is only stored in the const pmxops field
of a pinctrl_desc structure. Make the pinmux_ops structure const as
well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:41:23 +02:00
Julia Lawall
5bf7b849fb pinctrl: ingenic: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:41:05 +02:00
Julia Lawall
c3c9adfadc pinctrl: adi2: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:40:45 +02:00
Julia Lawall
0192fffec3 pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:40:25 +02:00
Julia Lawall
cfa5760c3b pinctrl: aspeed: g4: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops, and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:40:06 +02:00
Julia Lawall
db74f96d6a pinctrl: digicolor: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:39:36 +02:00
Julia Lawall
ecdc722f49 pinctrl: sirf: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:39:08 +02:00
Julia Lawall
71ccb82be7 pinctrl: sirf: atlas7: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinmux_ops structure is only stored in the const pmxops field
of a pinctrl_desc structure. Make the pinmux_ops structure const as
well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:38:46 +02:00
Julia Lawall
baf918c4ab pinctrl: st: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:38:03 +02:00
Julia Lawall
9b4e2ba424 pinctrl: armada-37xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinconf_ops structure is only stored in the const pinconf_ops
field of a pinctrl_desc structure. Make the pinconf_ops structure
const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:37:27 +02:00
Julia Lawall
d82a970009 pinctrl: artpec6: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinctrl_ops structure is only stored in the const pctlops
field of a pinctrl_desc structure. Make the pinctrl_ops structure
const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Lars Persson <lars.persson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:36:59 +02:00
Julia Lawall
7b2f016c3b pinctrl: bcm281xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinconf_ops structure is only stored in the const confops
field of a pinctrl_desc structure. Make the pinconf_ops structure
const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:36:25 +02:00
Katsuhiro Suzuki
abcac84fef pinctrl: uniphier: add Audio out pin-mux settings
The UniPhier LD11/20 SoC audio core use following 8 pins:
  AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2]

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:35:03 +02:00
David Daney
5a2a30024d gpio: Add gpio driver support for ThunderX and OCTEON-TX
Cavium ThunderX and OCTEON-TX are arm64 based SoCs.  Add driver for
the on-chip GPIO pins.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:28:22 +02:00
Gustavo A. R. Silva
2e6424ab85 pinctrl: amd: fix error return code in amd_gpio_probe()
platform_get_irq() returns an error code, but the pinctrl-amd driver
ignores it and always returns -EINVAL. This is not correct and,
prevents -EPROBE_DEFER from being propagated properly.

Print and propagate the return value of platform_get_irq on failure.

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:24:37 +02:00
Colin Ian King
27a451e83e drm/nouveau/kms/nv50: perform null check on msto[i] rathern than msto
The null check on the array msto is incorrect since msto is never
null. The null check should be instead on msto[i] since this is
being dereferenced in the call to drm_mode_connector_attach_encoder.

Thanks to Emil Velikov for pointing out the mistake in my original
fix and for suggesting the correct fix.

Detected by CoverityScan, CID#1375915 ("Array compared against 0")

Fixes: f479c0ba4a ("drm/nouveau/kms/nv50: initial support for DP 1.2 multi-stream")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:36 +10:00
Ilia Mirkin
bc60c90f47 drm/nouveau/pci/msi: disable MSI on big-endian platforms by default
It appears that MSI does not work on either G5 PPC nor on a E5500-based
platform, where other hardware is reported to work fine with MSI.

Both tests were conducted with NV4x hardware, so perhaps other (or even
this) hardware can be made to work. It's still possible to force-enable
with config=NvMSI=1 on load.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: stable@vger.kernel.org
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:36 +10:00
Ben Skeggs
2d38a5359f drm/nouveau: silence suspend/resume debugging messages
These are particularly annoying on Optimus systems where these paths can
be called regularly.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:36 +10:00
Ilia Mirkin
856718054a drm/nouveau/kms/nv04-nv4x: fix exposed format list
drm_crtc_init exposes the XRGB8888 and ARGB8888 formats. In actuality,
ARGB8888's 32-bit depth messes up some formulas that weren't meant for
it, and the alpha is fairly meaningless for the primary plane.

The modesetting logic appears to be fully prepared for RGB565 as well as
XRGB1555 however, as tested with modetest.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:35 +10:00
Ilia Mirkin
7fa620d577 drm/nouveau/kms/nv10-nv40: add NV21 support to overlay
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:35 +10:00
Ilia Mirkin
9a6edc3ac9 drm/nouveau/kms/nv04-nv40: improve overlay error detection, fix pitch setting
We were previously setting the pitch based on a perfectly packed buffer.
This does not necessarily happen. Either modetest started generating
such buffers recently, or earlier testing only happened with well-picked
overlay sizes.

While we're at it, beef up and refactor the error state detection.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:34 +10:00
Ilia Mirkin
3ce72bcf33 drm/nouveau/kms/nv04-nv40: prevent undisplayable framebuffers from creation
Pre-nv50 YUV overlays have stringent requirements for working with the
internal machinery. Instead of rejecting these at update_plane time, we
should instead prevent the framebuffers from being created in the first
place.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:34 +10:00
Ilia Mirkin
d257f9bf06 drm/nouveau/mpeg: print more debug info when rejecting dma objects
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:34 +10:00
Ben Skeggs
7a1af0f8bb drm/nouveau/fb/gf100-: zero mmu debug buffers
These are used for accesses to sparse mappings, and we want reads of
such mappings to return 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:33 +10:00
Ben Skeggs
485c2c91d4 drm/nouveau/bar/gf100: add config option to limit BAR2 to 16MiB
Useful for testing, and for the userspace build where we can't kick
a framebuffer driver off the device.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:33 +10:00
Ilia Mirkin
2659b4ce28 initial support (display-only) for GP108
Forked from GP107 implementation. Secboot/gr left out as we don't have
signed blobs from NVIDIA in linux-firmware.

(Ben): Was unable to mmiotrace the binary driver for unknown reasons,
       so not able to 100% confirm that no other changes from GP107
       are needed.  Quick testing shows it seems to work well enough
       for display.  Due to NVIDIA dragging their heels on getting
       signed firmware to us, this is the best we can do for now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101601
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:32 +10:00
Ben Skeggs
e20868b906 drm/nouveau/falcon: use a more reasonable msgqueue timeout value
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:32 +10:00
Rosen Penev
df00d5da60 drm/nouveau/disp: Silence DCB warnings.
Most of these errors seem to be WFD related. Official documentation
says dcb type 8 is reserved. It's probably used for WFD. Silence
the warning in either case.

Connector type 70 is stated to be a virtual connector for WiFi
display. Since we know this, don't warn that we don't.

Signed-off by: Rosen Penev <rosenp@gmail.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:32 +10:00
Rosen Penev
8190493244 drm/nouveau/bios: Demote missing fp table message to NV_DEBUG.
This warning seems to pop up mainly in laptop cards. Silence it as
it is expected behavior.

Signed-off by: Rosen Penev <rosenp@gmail.com>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:31 +10:00
Ben Skeggs
6b1277c837 drm/nouveau/pmu/gt215-: abstract detection of whether reset is needed
GT215, GF100-GP100, and GP10x are all different.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:31 +10:00
Ben Skeggs
715e7d261d drm/nouveau/pmu/gt215: fix reset
The NV_PMC_ENABLE bit for PMU did not appear until GF100, and some other
unknown register needs to be poked instead.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:30 +10:00
Ben Skeggs
1ccd7d52b1 drm/nouveau/mc/gf100: add pmu to reset mask
An upcoming commit will replace direct NV_PMC register bashing from PMU
with a call to the proper function.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:30 +10:00
Ilia Mirkin
eba5e56db6 drm/nouveau/disp/gf119-: avoid creating non-existent heads
We assume that each board has 4 heads for GF119+. However this is not
necessarily true - in the case of a GP108 board, the register indicated
that there were only 2.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101601
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:22 +10:00
Karol Herbst
9d60b9c9d0 drm/nouveau/therm/gm200: Added
This allows temperature readouts on maxwell2 GPUs.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:22 +10:00
Colin Ian King
4a84a6fd9a drm/nouveau/therm: fix spelling mistake on array thresolds
Array thresolds should be named thresholds, rename it. Also make it static
static const char * const

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-08-22 18:04:22 +10:00
Lee Jones
0f0fc5c090 Revert "mfd: da9061: Fix to remove BBAT_CONT register from chip model"
This patch was applied to the MFD twice, causing unwanted behavour.

This reverts commit b77eb79acc.

Fixes: b77eb79acc ("mfd: da9061: Fix to remove BBAT_CONT register from chip model")
Reported-by: Steve Twiss <stwiss.opensource@diasemi.com>
Reviewed-by: Steve Twiss <stwiss.opensource@diasemi.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-08-22 09:03:00 +01:00
Sebastian Reichel
4f16cab19a hwmon: da9052: Add support for TSI channel
TSI channel has a 4 channel mux connected to it and is normally
used for touchscreen support. The hardware may alternatively
use it as general purpose adc.

Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-08-22 08:45:02 +01:00
Sebastian Reichel
ebf555111b mfd: da9052: Make touchscreen registration optional
If the touchscreen pins are used as general purpose analogue
input, the touchscreen driver should not be used. The pins
will be handled by the existing hwmon driver instead.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-08-22 08:44:55 +01:00
Sebastian Reichel
7fe9899ef4 hwmon: da9052: Replace S_IRUGO with 0444
Fix checkpatch warnings about S_IRUGO being less readable than
providing the permissions octal as '0444'.

Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-08-22 08:44:46 +01:00
Christophe Jaillet
32e67b9af0 crypto: cavium/nitrox - Fix an error handling path in 'nitrox_probe()'
'err' is known to be 0 at this point.
If 'kzalloc()' fails, returns -ENOMEM instead of 0 which means success.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-08-22 14:54:55 +08:00
Christophe Jaillet
b7d65fe181 crypto: inside-secure - fix an error handling path in safexcel_probe()
'ret' is known to be 0 at this point.
If 'safexcel_request_ring_irq()' fails, it returns an error code.
Return this value instead of 0 which means success.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-08-22 14:54:55 +08:00
Zain Wang
5a7801f663 crypto: rockchip - Don't dequeue the request when device is busy
The device can only process one request at a time. So if multiple
requests came at the same time, we can enqueue them first, and
dequeue them one by one when the device is idle.

Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-08-22 14:54:54 +08:00
Corentin LABBE
baf5b752da crypto: cavium - add release_firmware to all return case
Two return case misses to call release_firmware() and so leak some
memory.

This patch create a fw_release label (and so a common error path)
and use it on all return case.

Detected by CoverityScan, CID#1416422 ("Resource Leak")

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-08-22 14:54:54 +08:00
Arvind Yadav
249cb06325 crypto: sahara - constify platform_device_id
platform_device_id are not supposed to change at runtime. All functions
working with platform_device_id provided by <linux/platform_device.h>
work with const platform_device_id. So mark the non-const structs as
const.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-08-22 14:54:53 +08:00
Lars Persson
a21eb94fc4 crypto: axis - add ARTPEC-6/7 crypto accelerator driver
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson <larper@axis.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-08-22 14:54:52 +08:00
Dave Airlie
b313f780de Merge tag 'drm-misc-fixes-2017-08-18' of git://anongit.freedesktop.org/git/drm-misc into drm-fixes
Core Changes:
- Fix framebuffer leak in setplane error condition (Nikil)
- Prevent BUG in atomic_ioctl by properly resetting state on EDEADLK (Maarten)
- Add missing return in atomic_check_only if atomic_check fails (Maarten)

Driver Changes:
- rockchip: Don't try to suspend if device not initialized (Jeffy)

Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
Cc: Nikhil Mahale <nmahale@nvidia.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

* tag 'drm-misc-fixes-2017-08-18' of git://anongit.freedesktop.org/git/drm-misc:
  drm/atomic: If the atomic check fails, return its value first
  drm/atomic: Handle -EDEADLK with out-fences correctly
  drm: Fix framebuffer leak
  drm/rockchip: Fix suspend crash when drm is not bound
2017-08-22 16:53:32 +10:00