Commit Graph

35517 Commits

Author SHA1 Message Date
Dave Airlie
e237dfe708 Merge tag 'drm-misc-next-2025-11-05-1' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.19-rc1:

UAPI Changes:
- Add userptr support to ivpu.
- Add IOCTL's for resource and telemetry data in amdxdna.

Core Changes:
- Improve some atomic state checking handling.
- drm/client updates.
- Use forward declarations instead of including drm_print.h
- RUse allocation flags in ttm_pool/device_init and allow specifying max
  useful pool size and propagate ENOSPC.
- Updates and fixes to scheduler and bridge code.
- Add support for quirking DisplayID checksum errors.

Driver Changes:
- Assorted cleanups and fixes in rcar-du, accel/ivpu, panel/nv3052cf,
  sti, imxm, accel/qaic, accel/amdxdna, imagination, tidss, sti,
  panthor, vkms.
- Add Samsung S6E3FC2X01 DDIC/AMS641RW, Synaptics TDDI series DSI,
  TL121BVMS07-00 (IL79900A) panels.
- Add mali MediaTek MT8196 SoC gpu support.
- Add etnaviv GC8000 Nano Ultra VIP r6205 support.
- Document powervr ge7800 support in the devicetree.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patch.msgid.link/5afae707-c9aa-4a47-b726-5e1f1aa7a106@linux.intel.com
2025-11-07 12:41:26 +10:00
Dave Airlie
8f037e11d0 Merge tag 'drm-intel-next-2025-11-04' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
drm/i915 feature pull for v6.19:

Features and functionality:
- Enable LNL+ content adaptive sharpness filter (CASF) (Nemesa)
- Use optimized VRR guardband (Ankit, Ville)
- Enable Xe3p LT PHY (Suraj)
- Enable FBC support for Xe3p_LPD display (Sai Teja, Vinod)
- Specify DMC firmware for display version 30.02 (Dnyaneshwar)
- Report reason for disabling PSR to debugfs (Michał)
- Extend i915_display_info with Type-C port details (Khaled)
- Log DSI send packet sequence errors and contents

Refactoring and cleanups:
- Refactoring to prepare for VRR guardband optimization (Ankit)
- Abstract VRR live status wait (Ankit)
- Refactor VRR and DSB timing to handle Set Context Latency explicitly (Ankit)
- Helpers for prefill latency calculations (Ville)
- Refactor SKL+ watermark latency setup (Ville)
- VRR refactoring and cleanups (Ville)
- SKL+ universal plane cleanups (Ville)
- Decouple CDCLK from state->modeset refactor (Ville)
- Refactor VLV/CHV clock functions (Jani)
- Refactor fbdev handling (Jani)
- Call i915 and xe runtime PM from display via function pointers (Jouni)
- IRQ code refactoring  (Jani)
- Drop display dependency on i915 feature check macros (Jani)
- Refactor and unify i915 and xe stolen memory interfaces towards display (Jani)
- Switch to driver agnostic drm to display pointer chase (Jani)
- Use display version over graphics version in display code (Matt A)
- GVT cleanups (Jonathan, Andi)
- Rename a VLV clock function to unify (Michał)
- Explicitly sanitize DMC package header num entries (Luca)
- Remove redundant port clock check from ALPM (Jouni)
- Use sysfs_emit() instead of sprintf() in PMU sysfs (Madhur Kumar)
- Clean up C20 PHY PLL register macros (Imre, Mika))
- Abstract "address in MMIO table" helper for general use (Matt A)
- Improve VRR platform abstractions (Ville)
- Move towards more standard PCI PM code usage (Ville)
- Framebuffer refactoring (Ville)
- Drop display dependency on i915_utils.h (Jani)
- Include cleanups (Jani)

Fixes:
- Workaround docking station DSC issues with high pixel clock and bpp (Imre)
- Fix Panel Replay in DSC mode (Imre)
- Disable tracepoints for PREEMPT_RT as a workaround (Maarten)
- Fix intel_crtc_get_vblank_counter() on PREEMPT_RT (Maarten)
- Fix C10 PHY identification on PTL/WCL (Dnyaneshwar)
- Take AS SDP into account with optimized guardband (Jouni)
- Fix panic structure allocation memory leak (Jani)
- Adjust an FBC workaround platforms (Vinod)
- Add fallback for CDCLK selection (Naladala)
- Avoid using invalid transcoder in MST transport select (Suraj)
- Don't use cursor size reduction on display version 14+ (Nemesa)
- Fix C20 PHY PLL register programming (Imre, Mika)
- Fix PSR frontbuffer flush handling (Jouni)
- Store ALPM parameters in crtc state (Jouni)
- Defeature DRRS on LNL+ (Ville)
- Fix the scope of the large DRAM DIMM workaround (Ville)
- Fix PICA vs. AUX power ordering issue (Gustavo)
- Fix pixel rate for computing watermark line time (Ville)
- Fix framebuffer set_tiling vs. addfb race (Ville)
- DMC event handler fixes (Ville)

DRM Core:
- CRTC sharpness strength property (Nemesa)
- DPCD DSC quirk for Synaptics Panamera devices (Imre)
- Helpers to query the branch DSC max throughput/line-width (Imre)

Merges:
- Backmerge drm-next for v6.18-rc and to sync with drm-xe-next (Jani)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/ec5a05f2df6d597a62033ee2d57225cce707b320@intel.com
2025-11-07 09:47:56 +10:00
Khaled Almahallawy
c4227e1609 drm/i915/display: Extend i915_display_info with Type-C port details
Expose key Type-C port data in i915_display_info to make it easier to
understand the port configuration and active mode, especially whether
the link is in DP-Alt or TBT-Alt, without having to scan kernel logs.

Tested in DP-Alt, TBT-Alt, SST, and MST.

Expected output:

[CONNECTOR:290:DP-2]: status: connected
	TC Port: E/TC#2 mode: tbt-alt pin assignment: - max lanes: 4
	physical dimensions: 600x340mm
...
[CONNECTOR:263:DP-5]: status: connected
	TC Port: G/TC#4 mode: dp-alt pin assignment: C max lanes: 4
	physical dimensions: 610x350mm

v2: Use drm_printer (Ville)
    Lock/Unlock around the printf (Imre)
v3: Forward Declaration drm_printer struct (Jani)
v4: Handle MST connector with no active encoder (Imre)
    Add a delimiter between fields and ":" after the port name (Imre)
v5: Init dig_port and use it in intel_encorder_is_tc and tc_info (Imre)
    Move tc->port_name to a newline (Imre)
v6: Use intel_tc_port_lock/Unlock (Imre)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251028190753.3089937-1-khaled.almahallawy@intel.com
2025-11-04 14:27:43 +02:00
Jouni Högander
98c7fc038c drm/i915/display: Use display parent interface for i915 runtime pm
Start using display parent interface for i915 runtime pm. Doing the same
for xe is done in coming changes.

v3:
  - remove useless include
v2:
  - use <> when including drm/intel/display_parent_interface.h
  - drop checks for validity of rpm function pointers

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patch.msgid.link/20251030202836.1815680-6-jouni.hogander@intel.com
2025-11-03 11:55:22 +02:00
Jouni Högander
5bef1badb3 drm/i915/display: Runtime pm wrappers for display parent interface
Implement runtime pm wrappers for i915 driver and add them into display
parent interface.

v2:
  - move i915 display rpm interface implementation to intel_runtime_pm.c
  - rename intel_display as i915_display

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patch.msgid.link/20251030202836.1815680-4-jouni.hogander@intel.com
2025-11-03 11:55:21 +02:00
Jani Nikula
b3c8fa0d9c drm/{i915, xe}/display: pass parent interface to display probe
Let's gradually start calling i915 and xe parent, or core, drivers from
display via function pointers passed at display probe.

Going forward, the struct intel_display_parent_interface is expected to
include const pointers to sub-structs by functionality, for example:

struct intel_display_rpm {
	struct ref_tracker *(*get)(struct drm_device *drm);
	/* ... */
};

struct intel_display_parent_interface {
	/* ... */
	const struct intel_display_rpm *rpm;
};

This is a baby step towards not building display as part of both i915
and xe drivers, but rather making it an independent driver interfacing
with the two.

v3: useless include additions dropped
v2: unrelated include removal dropped

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patch.msgid.link/20251030202836.1815680-2-jouni.hogander@intel.com
2025-11-03 11:55:19 +02:00
Suraj Kandpal
ad7108f966 drm/i915/ltphy: Modify the step that need to be skipped
Bspec has changed the non tbt pll enable sequence now we skip
steps 5-17 if no config change has occurred.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-26-suraj.kandpal@intel.com
2025-11-01 09:04:26 +05:30
Suraj Kandpal
e34c635694 drm/i915/display: Aux Enable and Display powerwell timeouts
From XE3P we can now poll if the AUX power is up or down define the
timeouts for each respectively.

Bspec: 68967
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-25-suraj.kandpal@intel.com
2025-11-01 09:04:24 +05:30
Suraj Kandpal
9dcf183632 drm/i915/ltphy: Define LT PHY PLL state verify function
Define function to verify the LT PHY PLL state function and call it
in intel_modeset_verify_crtc.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-24-suraj.kandpal@intel.com
2025-11-01 09:04:22 +05:30
Suraj Kandpal
89e0a91e89 drm/i915/ltphy: Define function to readout LT Phy PLL state
Define a function to readout hw state for LT Phy PLL which
can be used in get_config function call.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
2025-11-01 09:04:20 +05:30
Suraj Kandpal
3a6f155ce0 drm/i915/ltphy: Define the LT Phy state compare function
Define function to compare the state and if mismatch is detected
dump both the states.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-22-suraj.kandpal@intel.com
2025-11-01 09:04:18 +05:30
Suraj Kandpal
a54bdcb714 drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
We need to enable and disable the Tx for each active lane after the
Non-TBT enable sequence is done.

Bspec: 74500, 74497, 74701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-21-suraj.kandpal@intel.com
2025-11-01 09:04:17 +05:30
Suraj Kandpal
13ba213f92 drm/i915/ltphy: Program LT Phy Voltage Swing
Program LT Phy voltage swing using the Swing tables and plug in the
function at encoder->set_signal_level

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-20-suraj.kandpal@intel.com
2025-11-01 09:04:14 +05:30
Suraj Kandpal
c4b2da6dc1 drm/i915/ddi: Define LT Phy Swing tables
Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp.
HDMI TMDS is not needed since LT Phy H/w handles that.

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-19-suraj.kandpal@intel.com
2025-11-01 09:04:13 +05:30
Suraj Kandpal
109289252f drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
Hook up the LT Phy enable and disable sequences using encoder->
enable/disable_clock and reusing the TBT enable disable sequence from
cx0 PHY since it remains the same.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-18-suraj.kandpal@intel.com
2025-11-01 09:04:10 +05:30
Suraj Kandpal
fa5fd596bf drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
Program in the steps for Non TBT PLL disable sequence.
The whole function can be defined in one shot since most of
prequiste functions are already coded in.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-17-suraj.kandpal@intel.com
2025-11-01 09:04:08 +05:30
Suraj Kandpal
32865c2da5 drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
Program the rest of the LT Phy Non TBT PLL Enable sequence. This
can be done in a single patch since the rest of the prequistie
functions are already coded in.

Bspec: 74492, 69701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
2025-11-01 09:04:06 +05:30
Suraj Kandpal
82b4608323 drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
Program the rest of the steps with regards to PORT_CLOCK_CTL in
Non-TBT PLL enable sequence.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-15-suraj.kandpal@intel.com
2025-11-01 09:04:05 +05:30
Suraj Kandpal
41d07bd25a drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
Program the LT PHY P2P transaction which uses P2M cycle to get
get data fro Phy when it is ready and then go read the MAC register
from the MAC address space.

Bspec: 68966, 74497, 74483, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-14-suraj.kandpal@intel.com
2025-11-01 09:04:02 +05:30
Suraj Kandpal
2435a11d72 drm/i915/ltphy: Add function to calculate LT PHY port clock
Create a reverse algorithm which is used to find port clock
from the LT PHY state is provided which is used for
comparision & verification functions.

Bspec: 74667
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-13-suraj.kandpal@intel.com
2025-11-01 09:04:00 +05:30
Suraj Kandpal
3383ba2479 drm/i915/ltphy: Enable SSC during port clock programming
We enable SSC when we program PORT_CLOCK_CTL register. We logically
determine if ssc is enabled or not while we calculate our state.

Bspec: 74492, 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com
2025-11-01 09:03:59 +05:30
Suraj Kandpal
4f1118bf96 drm/i915/ltphy: Update the ltpll config table value for eDP
When we get the eDP tables we reuse dp tables for some data rates.
We need to modify the 3rd config value of this table to 1 instead
of 0 since that is the only difference in the dp and edp table for
that particular data rate.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-11-suraj.kandpal@intel.com
2025-11-01 09:03:58 +05:30
Suraj Kandpal
1dd885d509 drm/i915/ltphy: Program the VDR PLL registers for LT PHY
Fetch the tables which need to be used and program it in
the specified VDR register space. Everything is done over
the respective lanes.

Bspec: 68862, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
2025-11-01 09:03:56 +05:30
Suraj Kandpal
dc5742b619 drm/i915/ltphy: Add LT Phy Programming recipe tables
Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
function to use the correct table.

Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
2025-11-01 09:03:53 +05:30
Suraj Kandpal
e1455196ad drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
Read PHY_VDR_0_CONFIG to check if there is any change in the register and
decide based on that if P2P sequence to change the data rate of LT PHY
are required or not. This scenario only happens if the requested mode
uses 1.62Gbps with DP mode since LT PHY defaults to this mode if
any other mode is requested we need to follow the whole sequence.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
2025-11-01 09:03:51 +05:30
Suraj Kandpal
fc9be0a10c drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
Add a wrapper on cx0 powerdown change sequence for LT Phy usage,
as the sequence remains unchanged when going from SNPS Phy to
LT Phy.

Bspec: 74495
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
2025-11-01 09:03:49 +05:30
Suraj Kandpal
3a323c7e96 drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
Program sequence from port clock ctl except for the SSC
enablement part which will be taken care of later.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-6-suraj.kandpal@intel.com
2025-11-01 09:03:47 +05:30
Suraj Kandpal
809adb87da drm/i915/cx0: Move the HDMI FRL function to intel_hdmi
Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and
make it non static.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-5-suraj.kandpal@intel.com
2025-11-01 09:03:46 +05:30
Suraj Kandpal
154ebdb77a drm/i915/ltphy: Phy lane reset for LT Phy
Define function to bring phy lane out of reset for LT Phy and the
corresponding pre-requisite steps before we follow the steps for
Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence
function in which we can place this function

Bspec: 77449, 74749, 74499, 74495, 68960
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
2025-11-01 09:03:42 +05:30
Suraj Kandpal
66354f7f12 drm/i915/cx0: Change register bit naming for powerdown values
Change the register bit naming for powerdown values from CX0 to
XELPDP so that it can be used with LT Phy too.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-3-suraj.kandpal@intel.com
2025-11-01 09:03:40 +05:30
Suraj Kandpal
cff042eefe drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
Add LT Phy related VDR and pipe registers into its own new file.

Bspec: 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-2-suraj.kandpal@intel.com
2025-11-01 09:03:39 +05:30
Simona Vetter
dc1af502d5 Merge tag 'drm-intel-gt-next-2025-10-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes:

Fixes/improvements/new stuff:

- Set O_LARGEFILE in __create_shmem() (Taotao Chen)
- Fix incorrect error handling in shmem_pwrite() (Taotao Chen)
- Skip GuC communication warning on reset in progress [guc] (Zhanjun Dong)
- Fix conversion between clock ticks and nanoseconds [guc] (Umesh Nerlige Ramappa)

Miscellaneous:

- Avoid accessing uninitialized context in emit_rpcs_query() [selftests] (Krzysztof Karas)
- Fix typo in comment (I915_EXEC_NO_RELOC) [gem] (Marlon Henrique Sanches)

Backmerges:

- Merge drm/drm-next into drm-intel-gt-next (Joonas Lahtinen)

Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://patch.msgid.link/aQH994lQI_iVPzTI@linux
2025-10-31 18:57:55 +01:00
Vinod Govindapillai
5298eea7ed drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC
There is a hw restriction that we could enable the FBC for FP16
formats only if the pixel normalization block is enabled. Hence
enable the pixel normalizer block with normalzation factor as
1.0 for the supported FP16 formats to get the FBC enabled. Two
existing helper function definitions are moved up to avoid the
forward declarations as part of this patch as well.

v2: sw/hw state differentiation on handling pixel normalizer (Jani)

Bspec: 69863, 68881
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20251027134001.325064-5-vinod.govindapillai@intel.com
2025-10-31 13:32:16 +02:00
Vinod Govindapillai
aa1625abae drm/i915/xe3p_lpd: extract pixel format valid routine for FP16 formats
As the pixel normalizer block is needed only for the FP16 formats,
separating out the FP16 formats handling will benefit in selectively
enabling the pixel normalizer block in the following patch.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20251027134001.325064-4-vinod.govindapillai@intel.com
2025-10-31 13:32:16 +02:00
Vinod Govindapillai
5aa457874e drm/i915/xe3p_lpd: Add FBC support for FP16 formats
Add supported FP16 formats for FBC. FBC can be enabled with
FP16 formats only when plane pixel normalizer block is enabled.
The follow up patches will handle the pixel normalizer block
configuration.

v2: changes related to comments to use better tracking of pixel
    normalizer

Bspec: 6881, 69863, 68904
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20251027134001.325064-3-vinod.govindapillai@intel.com
2025-10-31 13:32:16 +02:00
Sai Teja Pottumuttu
ea5ce9afad drm/i915/xe3p_lpd: Extend FBC support to UINT16 formats
Starting Xe3p_LPD, FBC is supported on UINT16 formats as well. Also
UINT16 being a 64bpp format, will use cpp of 8 for cfb stride and thus
size calculations.

v2: simplify getting the cpp per format (Ville)
    simplify the pixel format is valid for xe3p_lp (Vinod)

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
BSpec: 68881, 68904, 69560
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20251027134001.325064-2-vinod.govindapillai@intel.com
2025-10-31 13:32:16 +02:00
Jani Nikula
b062cf5456 drm/i915/display: switch to intel_display_utils.h
The remaining utils display needs from i915_utils.h are primarily
MISSING_CASE() and fetch_and_zero(), with a couple of
i915_inject_probe_failure() uses.

To avoid excessive churn, add duplicates of MISSING_CASE() and
fetch_and_zero() to intel_display_utils.h, and switch display to use the
display utils.

As long as there are display files that include i915_drv.h, which
includes i915_utils.h, we'll need #ifndef guards for MISSING_CASE() and
fetch_and_zero() in both utils headers. We can remove them once display
no longer depends on i915_drv.h.

A couple of files in display still need i915_utils.h for
i915_inject_probe_failure(). Annotate this. They will be handled
separately.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link:  https://patch.msgid.link/79f9e31ca64c8c045834d48e20ceb0c515d1e9e1.1761146196.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 13:22:52 +02:00
Jani Nikula
aaccf0ba7e drm/i915/display: add intel_display_vtd_active()
Add intel_display_vtd_active() to utils. It's intentional duplication
with i915_utils.h i915_vtd_active(), but reduces duplication with
xe. Win some, lose some.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patch.msgid.link/e022166af7c67f43904e2d0fc87bc5c13e0f1204.1761146196.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 13:09:22 +02:00
Jani Nikula
cd81a70d76 drm/i915/display: add intel_display_run_as_guest()
Add intel_display_utils.c for display utilities that need more than a
header.

Start off with intel_display_run_as_guest(). The implementation is
intentional duplication of the i915_utils.h i915_run_as_guest(), with
the idea that it's small enough to not matter.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patch.msgid.link/469f9c41e0c3e3099314a3cf1a7671bf36ec8ffd.1761146196.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 13:09:10 +02:00
Jani Nikula
7c15791d19 drm/i915/display: create intel_display_utils.h
Start a file for display specific generic utilities.

Move KHz() and MHz() helpers there first.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patch.msgid.link/dbdd1915466850293b9737b751170dd225197873.1761146196.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 13:09:03 +02:00
Jani Nikula
00423c4a7d drm/i915: split out separate files for jiffies timeout and wait helpers
Add i915_jiffies.h and intel_display_jiffies.h for jiffies timeout and
wait helpers, and use them separately from i915 and display. This helps
reduce the display dependency on i915_utils.h.

Long term, both msecs_to_jiffies_timeout() and
wait_remaining_ms_from_jiffies() really belong in core kernel headers,
but for now unblock display refactoring.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patch.msgid.link/d8bc62b3a81afa05c849dde9b0f633572eaf5611.1761146196.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 13:08:48 +02:00
Jani Nikula
427c69c7d4 drm/i915/dsi: debug log send packet sequence contents
This might help debug issues better than just debug logging the function
name.

v2: Debug log type as hex (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251029084603.2254982-2-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 12:46:34 +02:00
Jani Nikula
23db1577ce drm/i915/dsi: log send packet sequence errors
We might be getting send packet sequence errors and never know. Log them
as errors. Also upgrade the not supported read commands to errors.

v2: Also error log -EOPNOTSUPP (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251029084603.2254982-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-31 12:46:34 +02:00
Tvrtko Ursulin
77e19f8d32 drm/ttm: Replace multiple booleans with flags in device init
Multiple consecutive boolean function arguments are usually not very
readable.

Replace the ones in ttm_device_init() with flags with the additional
benefit of soon being able to pass in more data with just a one off
code base churning cost.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Danilo Krummrich <dakr@kernel.org>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Lyude Paul <lyude@redhat.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sui Jingfeng <suijingfeng@loongson.cn>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: Zack Rusin <zack.rusin@broadcom.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Zack Rusin <zack.rusin@broadcom.com>
Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> # For xe
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Link: https://lore.kernel.org/r/20251020115411.36818-4-tvrtko.ursulin@igalia.com
[tursulin: fixup checkpatch while applying]
2025-10-31 09:14:35 +00:00
Jani Nikula
f6e8dc9edf drm: include drm_print.h where needed
There are a gazillion files that depend on drm_print.h being indirectly
included via drm_buddy.h, drm_mm.h, or ttm/ttm_resource.h. In
preparation for removing those includes, explicitly include drm_print.h
where needed.

Cc: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/5fe67395907be33eb5199ea6d540e29fddee71c8.1761734313.git.jani.nikula@intel.com
2025-10-31 10:34:52 +02:00
Nemesa Garg
7460b69f1d drm/i915/display: Expose sharpness strength property
Expose the drm crtc sharpness strength property which will enable
or disable the sharpness/casf based on user input. With this user
can set/update the strength of the sharpness or casf filter.

v2: Update subject[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-11-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30 15:44:38 +02:00
Nemesa Garg
39f39d2e9d drm/i915/display: Enable/disable casf
Call intel_casf_enable and intel_casf_disable
in atomic commit path to enable and disable casf.
Call intel_casf_update_strength to only update
the desired strength value.

v2: Introduce casf_enable here.[Ankit]
v3: Use is_disabling in casf_disabling.[Ankit]
v4: Swap old_state and new_state param.[Ankit]
v5: In disable fn move win_sz after sharpness_ctl.
v6: Rebase and update commit message.

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-10-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30 15:44:32 +02:00
Nemesa Garg
5f331b2452 drm/i915/display: Set and get the casf config
Set the configuration for CASF and capture it
in crtc_state and get the configuration by
reading back. Add the support to compare the
software and hardware state of CASF.

v2: Update subject[Ankit]
v3: Add the state compare[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-9-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30 15:44:25 +02:00
Nemesa Garg
0672cf9828 drm/i915/display: Configure the second scaler
Both sharpness and panel fitter use pipe scaler,
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler is available and make sure that only
either of panel fitter or sharpness is enabled at
a time.

v2: Add the panel fitting check before enabling sharpness
v3: Reframe commit message[Arun]
v4: Replace string based comparison with plane_state[Jani]
v5: Rebase
v6: Fix build issue
v7: Remove scaler id from verify_crtc_state[Ankit]
v8: Change the patch title. Add code comment.
    Move the config part in patch#6. [Ankit]
v9: Refactor the patch[Ankit]
v10: Modify the header of patch[Ankit]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-8-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30 15:44:02 +02:00
Nemesa Garg
82860cba5f drm/i915/display: Add and compute scaler parameter
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.

v1: Rename the title of patch [Ankit]
v2: Remove setup_casf from here[Ankit]
v3: Add skl_scaler_setup_casf in casf_enable

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-7-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30 15:43:24 +02:00