From bec6ba4cdf2ac918364836c54f7d6deaf280bcb8 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Thu, 19 Nov 2015 17:19:31 -0600 Subject: [PATCH 01/30] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC Add initial dts files and SoC support for IPQ4019 Signed-off-by: Varadarajan Narayanan Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 ++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi new file mode 100644 index 000000000000..fc738228c59a --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "skeleton.dtsi" +#include + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019"; + compatible = "qcom,ipq4019"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + }; + }; + + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq4019"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x1800000 0x60000>; + }; + + tlmm: pinctrl@0x01000000 { + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + }; + + serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = <0 107 0>; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + }; + + serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + }; + }; +}; From dbe9e6f6451929b5beb7e8ec6a8d4193e698636a Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Thu, 19 Nov 2015 17:19:32 -0600 Subject: [PATCH 02/30] dts: ipq4019: Add support for IPQ4019 DK01 board Initial board support dts files for DK01 board. Signed-off-by: Senthilkumar N L Signed-off-by: Varadarajan Narayanan Signed-off-by: Andy Gross --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +++++++ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 59 +++++++++++++++++++ 3 files changed, 82 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 95c1923ce6fa..15ed1221b4d4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -546,6 +546,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ + qcom-ipq4019-ap.dk01.1-c1.dtb \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts new file mode 100644 index 000000000000..0d92f1bc3a13 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "qcom-ipq4019-ap.dk01.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; + +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi new file mode 100644 index 000000000000..fe78f3f2c919 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -0,0 +1,59 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "qcom-ipq4019.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; + compatible = "qcom,ipq4019"; + + clocks { + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + }; + + soc { + + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <48000000>; + }; + + pinctrl@0x01000000 { + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + }; + + serial@78af000 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + }; +}; From 595b30c716d57cd4b61054de338bf834fc7a351e Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Thu, 19 Nov 2015 18:29:48 -0600 Subject: [PATCH 03/30] qcom: ipq4019: add acc and saw nodes to bring up secondary cores This adds the required device tree nodes to bring up the secondary cores on the ipq4019 SoC. Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index fc738228c59a..e44f5b6a1c76 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -27,29 +27,45 @@ cpus { cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; }; @@ -92,6 +108,50 @@ tlmm: pinctrl@0x01000000 { interrupts = <0 208 0>; }; + acc0: clock-controller@b088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; + }; + + acc1: clock-controller@b098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; + }; + + acc2: clock-controller@b0a8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; + }; + + acc3: clock-controller@b0b8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; + }; + + saw0: regulator@b089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw1: regulator@b099000 { + compatible = "qcom,saw2"; + reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw2: regulator@b0a9000 { + compatible = "qcom,saw2"; + reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw3: regulator@b0b9000 { + compatible = "qcom,saw2"; + reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; From 40057afdc2a02e488a3556dedd8383f86751d006 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:05 -0500 Subject: [PATCH 04/30] qcom: ipq4019: add watchdog node to ipq4019 SoC and DK01 device tree This will allow boards to enable watchdog support Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 ++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index fe78f3f2c919..223da1afd89a 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -55,5 +55,9 @@ serial@78af000 { pinctrl-names = "default"; status = "ok"; }; + + watchdog@b017000 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index e44f5b6a1c76..00a5e9ef95ea 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -171,5 +171,13 @@ serial@78b0000 { <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; }; + + watchdog@b017000 { + compatible = "qcom,kpss-standalone"; + reg = <0xb017000 0x40>; + clocks = <&sleep_clk>; + timeout-sec = <10>; + status = "disabled"; + }; }; }; From 8196dd5e5c4c3b623a23e25060588a7129f0574e Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:06 -0500 Subject: [PATCH 05/30] qcom: ipq4019: add support for reset via qcom,ps-hold This will allow these types of boards to be rebooted. Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 00a5e9ef95ea..acb851d55a19 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -179,5 +179,10 @@ watchdog@b017000 { timeout-sec = <10>; status = "disabled"; }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; }; }; From 13ad4fd36a815f1f4fb96c7308ea104bafc6bdb9 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:07 -0500 Subject: [PATCH 06/30] qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree This will allow boards to enable the SPI bus Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 37 +++++++++++++++++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 +++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 223da1afd89a..21032a8c86f6 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -48,6 +48,43 @@ mux { bias-disable; }; }; + + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio54"; + }; + pinconf { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio54"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + spi_0: spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "ok"; + cs-gpios = <&tlmm 54 0>; + + mx25l25635e@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "mx25l25635e"; + spi-max-frequency = <24000000>; + }; }; serial@78af000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb851d55a19..99e64f4881bc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -15,12 +15,18 @@ #include "skeleton.dtsi" #include +#include +#include / { model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; + aliases { + spi0 = &spi_0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -108,6 +114,18 @@ tlmm: pinctrl@0x01000000 { interrupts = <0 208 0>; }; + spi_0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + acc0: clock-controller@b088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; From e76b4284b520ba3b83d2f3df1451c0cbb897b85d Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:08 -0500 Subject: [PATCH 07/30] qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree This will allow boards to enable the I2C bus CC: Sricharan R Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 99e64f4881bc..1937edfdcd75 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -25,6 +25,7 @@ / { aliases { spi0 = &spi_0; + i2c0 = &i2c_0; }; cpus { @@ -126,6 +127,18 @@ spi_0: spi@78b5000 { status = "disabled"; }; + i2c_0: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b7000 0x6000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + acc0: clock-controller@b088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; From 15689ec209b2bc9ef0a02a82fdafd6da87dc1021 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:10 -0500 Subject: [PATCH 08/30] qcom: ipq4019: add cpu operating points for cpufreq support This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 1937edfdcd75..db48fd348370 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -40,6 +40,14 @@ cpu@0 { reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@1 { From fd6fd38692171e12aff2ef3ae854de24b1c3a3df Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:11 -0500 Subject: [PATCH 09/30] qcom: ipq4019: add crypto nodes to ipq4019 SoC and DK01 device tree This adds the crypto nodes to the ipq4019 device tree, it also adds the BAM node used by crypto as well which the driver currently requires to operate properly The crypto driver itself depends on some other patches to qcom_bam_dma to function properly: https://lkml.org/lkml/2015/12/1/113 CC: Stanimir Varbanov Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 ++++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 21032a8c86f6..2c347ad8faab 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -93,6 +93,14 @@ serial@78af000 { status = "ok"; }; + cryptobam: dma@8e04000 { + status = "ok"; + }; + + crypto@8e3a000 { + status = "ok"; + }; + watchdog@b017000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index db48fd348370..3cd42c04421b 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -147,6 +147,31 @@ i2c_0: i2c@78b7000 { status = "disabled"; }; + + cryptobam: dma@8e04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x08e04000 0x20000>; + interrupts = ; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + status = "disabled"; + }; + + crypto@8e3a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x08e3a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + acc0: clock-controller@b088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; From 9ca595f08e021972e6113dacf06b247a71e09530 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 23 Mar 2016 17:05:12 -0500 Subject: [PATCH 10/30] qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree This adds the blsp_dma node to the device tree and the required properties for using DMA with serial Signed-off-by: Matthew McClintock Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 ++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 2c347ad8faab..b9457dd21a69 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -72,6 +72,10 @@ pinconf_cs { }; }; + blsp_dma: dma@7884000 { + status = "ok"; + }; + spi_0: spi@78b5000 { pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 3cd42c04421b..5c08d19066c2 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -123,6 +123,17 @@ tlmm: pinctrl@0x01000000 { interrupts = <0 208 0>; }; + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + spi_0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x78b5000 0x600>; @@ -224,6 +235,8 @@ serial@78af000 { clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; }; serial@78b0000 { @@ -234,6 +247,8 @@ serial@78b0000 { clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; }; watchdog@b017000 { From 973111981b2de97c22891f83b76981dc27b42202 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Mar 2016 18:32:37 -0700 Subject: [PATCH 11/30] ARM: dts: msm8974: Split efs in rfsa and rmtfs One part of the efs memory region is used specifically for sharing file system buffers between the apps and modem cpus (aka rmtfs), so better reflect this split. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ef5330578431..8780246bd3c1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -49,8 +49,13 @@ tz@0fc00000 { no-map; }; - efs@0fd600000 { - reg = <0x0fd60000 0x1a0000>; + rfsa@0fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@0fd80000 { + reg = <0x0fd80000 0x180000>; no-map; }; From 89af1c2d63b0e9785e11e17c1435825c56705052 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Mar 2016 18:32:38 -0700 Subject: [PATCH 12/30] ARM: dts: msm8974: Add node for second i2c from blsp1 Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8780246bd3c1..d8078d350ede 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -445,6 +445,17 @@ msmgpio: pinctrl@fd510000 { interrupts = <0 208 0>; }; + i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = <0 96 IRQ_TYPE_NONE>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp_i2c8: i2c@f9964000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; From 5d3178c82739ae052d442b2fc8c332ce6fb4c7c9 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Mar 2016 18:32:39 -0700 Subject: [PATCH 13/30] ARM: dts: msm8974: Add modem smp2p and smd nodes Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d8078d350ede..e98b3738ee42 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -168,6 +168,31 @@ smem { hwlocks = <&tcsr_mutex 3>; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-wcnss { compatible = "qcom,smp2p"; qcom,smem = <451>, <431>; @@ -510,6 +535,13 @@ blsp2_dma: dma-controller@f9944000 { smd { compatible = "qcom,smd"; + modem { + interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 12>; + qcom,smd-edge = <0>; + }; + rpm { interrupts = <0 168 1>; qcom,ipc = <&apcs 8 0>; From b9e4c5e6ee26a906fa8514467b5abb9655c3ffdc Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Mar 2016 20:37:02 -0700 Subject: [PATCH 14/30] ARM: dts: qcom: apq8064: Add syscon for sic-non-secure Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 65d0e8d98259..4dc7e2c740af 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -212,6 +212,11 @@ saw3: power-controller@20b9000 { regulator; }; + sps_sic_non_secure: sps-sic-non-secure@12100000 { + compatible = "syscon"; + reg = <0x12100000 0x10000>; + }; + gsbi1: gsbi@12440000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; From b4d4582fa6959ee494b2146522f1edd72ba6218d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Mar 2016 20:37:03 -0700 Subject: [PATCH 15/30] ARM: dts: qcom: apq8064: Add complete smsm node Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 49 +++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 4dc7e2c740af..24c3c3581917 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -124,6 +124,55 @@ smem { hwlocks = <&sfpb_mutex 3>; }; + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&l2cc 8 4>; + qcom,ipc-2 = <&l2cc 8 14>; + qcom,ipc-3 = <&l2cc 8 23>; + qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + q6_smsm: q6@2 { + reg = <2>; + interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@3 { + reg = <3>; + interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + dsps_smsm: dsps@4 { + reg = <4>; + interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; From 2afc5287c50e013c46e07413c066920dc7f55a91 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 28 Mar 2016 20:37:04 -0700 Subject: [PATCH 16/30] ARM: dts: qcom: apq8064: Add smd node and all edges Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 40 +++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 24c3c3581917..042a8903bdb1 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -124,6 +124,46 @@ smem { hwlocks = <&sfpb_mutex 3>; }; + smd { + compatible = "qcom,smd"; + + modem@0 { + interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 3>; + qcom,smd-edge = <0>; + + status = "disabled"; + }; + + q6@1 { + interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 15>; + qcom,smd-edge = <1>; + + status = "disabled"; + }; + + dsps@3 { + interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&sps_sic_non_secure 0x4080 0>; + qcom,smd-edge = <3>; + + status = "disabled"; + }; + + riva@6 { + interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 25>; + qcom,smd-edge = <6>; + + status = "disabled"; + }; + }; + smsm { compatible = "qcom,smsm"; From 67b5ad57df3537aa479010af1581e8c4edf580e4 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:50 +0100 Subject: [PATCH 17/30] ARM: dts: apq8064: fix the pinctrls for i2c and spi This patch fixes pinctrls for spi and i2c nodes whose default and sleep states are together, which is incorrect. Without this patch i2c/spi would not be functional. Signed-off-by: Srinivas Kandagatla Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 042a8903bdb1..18637c06566c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -321,7 +321,8 @@ gsbi1: gsbi@12440000 { gsbi1_i2c: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x12460000 0x1000>; interrupts = <0 194 IRQ_TYPE_NONE>; @@ -349,7 +350,8 @@ gsbi2: gsbi@12480000 { gsbi2_i2c: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; - pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_pins_sleep>; pinctrl-names = "default", "sleep"; interrupts = <0 196 IRQ_TYPE_NONE>; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; @@ -371,7 +373,8 @@ gsbi3: gsbi@16200000 { ranges; gsbi3_i2c: i2c@16280000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&i2c3_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x16280000 0x1000>; interrupts = ; @@ -396,7 +399,8 @@ gsbi4: gsbi@16300000 { gsbi4_i2c: i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x16380000 0x1000>; interrupts = ; @@ -431,7 +435,8 @@ gsbi5_spi: spi@1a280000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; interrupts = <0 155 0>; - pinctrl-0 = <&spi5_default &spi5_sleep>; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; pinctrl-names = "default", "sleep"; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -464,7 +469,8 @@ gsbi6_serial: serial@16540000 { gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-1 = <&i2c6_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x16580000 0x1000>; interrupts = ; From 12861674c99100b77dc78ed5037e4e1a5b95b0d5 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:51 +0100 Subject: [PATCH 18/30] ARM: dts: apq8064: add support to gsbi1 uart This patch adds support to gsbi1 uart and its pinctrls nodes. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 10 ++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index b57c59d5bc00..8bb5e5f3d07a 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -39,6 +39,20 @@ pinconf { }; }; + gsbi1_uart_2pins: gsbi1_uart_2pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi1"; + }; + }; + + gsbi1_uart_4pins: gsbi1_uart_4pins { + mux { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + i2c2_pins: i2c2 { mux { pins = "gpio24", "gpio25"; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 18637c06566c..407a072dea69 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -319,6 +319,16 @@ gsbi1: gsbi@12440000 { syscon-tcsr = <&tcsr>; + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 0x0>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + gsbi1_i2c: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; pinctrl-0 = <&i2c1_pins>; From e4b01fda5dca99c227494bd9dc3a9d7628a17c2f Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:52 +0100 Subject: [PATCH 19/30] ARM: dts: apq8064: add gsbi7 i2c support This patch adds support to gsbi7 i2c which is used in some of the new boards. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 25 ++++++++++++++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 13 ++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index 8bb5e5f3d07a..4102a98f475b 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -219,4 +219,29 @@ mux { function = "gsbi7"; }; }; + + i2c7_pins: i2c7 { + mux { + pins = "gpio84", "gpio85"; + function = "gsbi7"; + }; + + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c7_pins_sleep: i2c7_pins_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 407a072dea69..b176c094cd6f 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -511,6 +511,19 @@ gsbi7_serial: serial@16640000 { clock-names = "core", "iface"; status = "disabled"; }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c7_pins>; + pinctrl-1 = <&i2c7_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16680000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; rng@1a500000 { From 973747fb473474db4ad69900e7af7d4f91e78895 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:53 +0100 Subject: [PATCH 20/30] ARM: dts: db600c: add board support with serial This patch adds support to DB600c with basic serial ports. DB600c is based on APQ8064. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/qcom-apq8064-arrow-db600c.dts | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 15ed1221b4d4..8904a0a1cdf6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -539,6 +539,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-arrow-db600c.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-yuga.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts new file mode 100644 index 000000000000..57d45001cc27 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -0,0 +1,36 @@ +#include "qcom-apq8064-v2.0.dtsi" + +/ { + model = "Arrow Electronics, APQ8064 DB600c"; + compatible = "arrow,db600c", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi1_serial; + }; + + soc { + gsbi@12440000 { + status = "okay"; + qcom,mode = ; + serial@12450000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi1_uart_4pins>; + }; + }; + + /* DEBUG UART */ + gsbi@16600000 { + status = "okay"; + qcom,mode = ; + serial@16640000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi7_uart_2pins>; + }; + }; + }; +}; From 696a8a16f92b83c14c58b7a4d28526aaeeabafe8 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:54 +0100 Subject: [PATCH 21/30] ARM: dts: db600c: add pmic regulator supplies This patch adds pmic regulator supplies connected on the board. Rest of the invidual regulators would be added as and when required by the devices. Signed-off-by: Srinivas Kandagatla Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../boot/dts/qcom-apq8064-arrow-db600c.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 57d45001cc27..6695b007a34f 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -9,7 +9,69 @@ aliases { serial1 = &gsbi1_serial; }; + regulators { + compatible = "simple-bus"; + vph: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-boot-on; + }; + }; + soc { + rpm@108000 { + regulators { + vdd_s1-supply = <&vph>; + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + vdd_s5-supply = <&vph>; + vdd_s6-supply = <&vph>; + vdd_s7-supply = <&vph>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l3_l15_l17-supply = <&vph>; + vdd_l4_l14-supply = <&vph>; + vdd_l5_l8_l16-supply = <&vph>; + vdd_l6_l7-supply = <&vph>; + vdd_l9_l11-supply = <&vph>; + vdd_l10_l22-supply = <&vph>; + vdd_l21_l23_l29-supply = <&vph>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + regulator-always-on; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + }; + }; + gsbi@12440000 { status = "okay"; qcom,mode = ; From 226355fb9e486ae472df10e34eb5ac636f196657 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:55 +0100 Subject: [PATCH 22/30] ARM: dts: db600c: Add eMMC and SD card support This patch adds eMMC and SD card support with card detect and adding required regulators. Signed-off-by: Srinivas Kandagatla Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-apq8064-arrow-db600c-pins.dtsi | 9 +++++ .../boot/dts/qcom-apq8064-arrow-db600c.dts | 34 +++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi new file mode 100644 index 000000000000..7339919783d2 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi @@ -0,0 +1,9 @@ +&tlmm_pinmux { + card_detect: card-detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 6695b007a34f..d92142409c43 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -1,4 +1,6 @@ #include "qcom-apq8064-v2.0.dtsi" +#include "qcom-apq8064-arrow-db600c-pins.dtsi" +#include / { model = "Arrow Electronics, APQ8064 DB600c"; @@ -69,6 +71,20 @@ s7 { regulator-max-microvolt = <1300000>; qcom,switch-mode-frequency = <3200000>; }; + + l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + regulator-boot-on; + regulator-always-on; + }; + + l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; }; }; @@ -94,5 +110,23 @@ serial@16640000 { pinctrl-0 = <&gsbi7_uart_2pins>; }; }; + + amba { + /* eMMC */ + sdcc@12400000 { + status = "okay"; + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + }; + + /* External micro SD card */ + sdcc@12180000 { + status = "okay"; + vmmc-supply = <&pm8921_l6>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + }; }; }; From f43a92715d5b71b3524a96bdf3b5ed6c4ce1d6b2 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:56 +0100 Subject: [PATCH 23/30] ARM: dts: db600c: add usb support This patch adds usb host and otg support on board with required regulators. Signed-off-by: Srinivas Kandagatla Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../boot/dts/qcom-apq8064-arrow-db600c.dts | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index d92142409c43..2c563df3c832 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -58,6 +58,12 @@ s1 { bias-pull-down; }; + s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -72,6 +78,18 @@ s7 { qcom,switch-mode-frequency = <3200000>; }; + l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + l5 { regulator-min-microvolt = <2750000>; regulator-max-microvolt = <3000000>; @@ -85,6 +103,12 @@ l6 { regulator-max-microvolt = <2950000>; bias-pull-down; }; + + l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; }; }; @@ -111,6 +135,46 @@ serial@16640000 { }; }; + /* OTG */ + phy@12500000 { + status = "okay"; + dr_mode = "peripheral"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + + phy@12520000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + phy@12530000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + gadget@12500000 { + status = "okay"; + }; + + /* OTG */ + usb@12500000 { + status = "okay"; + }; + + usb@12520000 { + status = "okay"; + }; + + usb@12530000 { + status = "okay"; + }; + amba { /* eMMC */ sdcc@12400000 { From c22847863a58c42035660ffa7fadbef6459e67bd Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:57 +0100 Subject: [PATCH 24/30] ARM: dts: db600c: add pcie support This patch adds pcie and regulators required to get on board ATL1C ethernet working. Signed-off-by: Srinivas Kandagatla Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-apq8064-arrow-db600c-pins.dtsi | 12 ++++++++++ .../boot/dts/qcom-apq8064-arrow-db600c.dts | 24 +++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi index 7339919783d2..0610f0027b38 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi @@ -6,4 +6,16 @@ mux { bias-disable; }; }; + + pcie_pins: pcie-pinmux { + mux { + pins = "gpio27"; + function = "gpio"; + }; + conf { + pins = "gpio27"; + drive-strength = <12>; + bias-disable; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 2c563df3c832..4f2218c4622e 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -21,6 +21,16 @@ vph: regulator-fixed@1 { regulator-type = "voltage"; regulator-boot-on; }; + + /* on board fixed 3.3v supply */ + vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; soc { @@ -109,6 +119,10 @@ l23 { regulator-max-microvolt = <1900000>; bias-pull-down; }; + + lvs6 { + bias-pull-down; + }; }; }; @@ -135,6 +149,16 @@ serial@16640000 { }; }; + pci@1b500000 { + status = "okay"; + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&vcc3v3>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; + /* OTG */ phy@12500000 { status = "okay"; From 2ce36229a8cab110d50f227dda64850072e74b2d Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:58 +0100 Subject: [PATCH 25/30] ARM: dts: db600c: add on board sata support. This patch enables sata and regulators required to get on board sata working. Signed-off-by: Srinivas Kandagatla Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 4f2218c4622e..6f97ddc340e6 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -123,6 +123,10 @@ l23 { lvs6 { bias-pull-down; }; + + lvs7 { + bias-pull-down; + }; }; }; @@ -159,6 +163,15 @@ pci@1b500000 { perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; + phy@1b400000 { + status = "okay"; + }; + + sata@29000000 { + status = "okay"; + target-supply = <&pm8921_lvs7>; + }; + /* OTG */ phy@12500000 { status = "okay"; From 2f29160fce634cb0e8e1bc493d0e509407ac1e0e Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:33:59 +0100 Subject: [PATCH 26/30] ARM: dts: db600c: Add on board leds support This patch adds support to 4 user leds, wlan and bt led on board. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- .../dts/qcom-apq8064-arrow-db600c-pins.dtsi | 23 +++++++++ .../boot/dts/qcom-apq8064-arrow-db600c.dts | 47 +++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi index 0610f0027b38..3b55bb97c696 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi @@ -18,4 +18,27 @@ conf { bias-disable; }; }; + + user_leds: user-leds { + mux { + pins = "gpio3", "gpio7", "gpio10", "gpio11"; + function = "gpio"; + }; + + conf { + pins = "gpio3", "gpio7", "gpio10", "gpio11"; + function = "gpio"; + output-low; + }; + }; +}; + +&pm8921_mpps { + mpp_leds: mpp-leds { + pinconf { + pins = "mpp7", "mpp8"; + function = "digital"; + output-low; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 6f97ddc340e6..8c18a4bad088 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -153,6 +153,53 @@ serial@16640000 { }; }; + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>, <&mpp_leds>; + + compatible = "gpio-leds"; + + user-led0 { + label = "user0-led"; + gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "user1-led"; + gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "user2-led"; + gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + user-led3 { + label = "user3-led"; + gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + wifi-led { + label = "WiFi-led"; + gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + bt-led { + label = "BT-led"; + gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + pci@1b500000 { status = "okay"; vdda-supply = <&pm8921_s3>; From d8aef8720c605600e21f57c412876f60e1721582 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:34:00 +0100 Subject: [PATCH 27/30] ARM: dts: db600c: add i2c support This patch adds nodes required to enable 4 i2c buses on the board which are connected to various sensors and eeprom. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- .../boot/dts/qcom-apq8064-arrow-db600c.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 8c18a4bad088..2f0dfff75572 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -9,6 +9,10 @@ / { aliases { serial0 = &gsbi7_serial; serial1 = &gsbi1_serial; + i2c0 = &gsbi2_i2c; + i2c1 = &gsbi3_i2c; + i2c2 = &gsbi4_i2c; + i2c3 = &gsbi7_i2c; }; regulators { @@ -141,6 +145,42 @@ serial@12450000 { }; }; + gsbi@12480000 { + status = "okay"; + qcom,mode = ; + i2c@124a0000 { + /* On Low speed expansion and Sensors */ + label = "LS-I2C0"; + status = "okay"; + }; + }; + + gsbi@16200000 { + status = "okay"; + qcom,mode = ; + i2c@16280000 { + /* On Low speed expansion */ + status = "okay"; + label = "LS-I2C1"; + clock-frequency = <200000>; + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <64>; + }; + }; + }; + + gsbi@16300000 { + status = "okay"; + qcom,mode = ; + i2c@16380000 { + /* On High speed expansion */ + label = "HS-CAM-I2C3"; + status = "okay"; + }; + }; + /* DEBUG UART */ gsbi@16600000 { status = "okay"; @@ -151,6 +191,12 @@ serial@16640000 { pinctrl-names = "default"; pinctrl-0 = <&gsbi7_uart_2pins>; }; + + i2c@16680000 { + /* On High speed expansion */ + status = "okay"; + label = "HS-CAM-I2C2"; + }; }; leds { From e0da214a8892d0e36f8575e1c996e78c66e2674c Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:34:01 +0100 Subject: [PATCH 28/30] ARM: dts: db600c: add spi support This patch adds spi nodes required to provide spi bus support on LS expansion. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 2f0dfff75572..34bb4157872e 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -13,6 +13,7 @@ aliases { i2c1 = &gsbi3_i2c; i2c2 = &gsbi4_i2c; i2c3 = &gsbi7_i2c; + spi0 = &gsbi5_spi; }; regulators { @@ -181,6 +182,15 @@ i2c@16380000 { }; }; + gsbi@1a200000 { + status = "okay"; + spi@1a280000 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; + }; + }; + /* DEBUG UART */ gsbi@16600000 { status = "okay"; From 2b9d49d8c749ce3c8f5cb28f54875a6f33fa1f72 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 12 Apr 2016 10:34:02 +0100 Subject: [PATCH 29/30] ARM: dts: db600c: add support to magnetometer This patch adds support to on board LIS3MDLTR magnetometer. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- .../boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi | 8 ++++++++ arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts | 13 +++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi index 3b55bb97c696..a3efb9704fcd 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi @@ -31,6 +31,14 @@ conf { output-low; }; }; + + magneto_pins: magneto-pins { + mux { + pins = "gpio31", "gpio48"; + function = "gpio"; + bias-disable; + }; + }; }; &pm8921_mpps { diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts index 34bb4157872e..e01b27ea7fba 100644 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -153,6 +153,19 @@ i2c@124a0000 { /* On Low speed expansion and Sensors */ label = "LS-I2C0"; status = "okay"; + lis3mdl_mag@1e { + compatible = "st,lis3mdl-magn"; + reg = <0x1e>; + vdd-supply = <&vcc3v3>; + vddio-supply = <&pm8921_s4>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_pins>; + interrupt-parent = <&tlmm_pinmux>; + + st,drdy-int-pin = <2>; + interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ + <31 IRQ_TYPE_EDGE_RISING>; /* INT */ + }; }; }; From 3db63602505fa30f9d8faa1512fc71dae0cbf71b Mon Sep 17 00:00:00 2001 From: John Stultz Date: Thu, 14 Apr 2016 14:07:11 -0700 Subject: [PATCH 30/30] device-tree: nexus7: Add bq27541 battery interface to dts Add support for battery level reading on the Nexus7 by enabling the bq27541 driver in the nexus7 dts Cc: Rob Herring Cc: Arnd Bergmann Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Andy Gross Cc: Vinay Simha BN Cc: Bjorn Andersson Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Acked-by: Rob Herring Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index c535b3f0e5cf..32fedfa149d0 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -224,6 +224,12 @@ eeprom@52 { reg = <0x52>; pagesize = <32>; }; + + bq27541@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; + }; };