From 4d6952981244d1e455e2469cfd93e3b5eaddc4a7 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 20 Feb 2025 15:01:04 +0000 Subject: [PATCH 1/6] clk: renesas: r9a09g057: Add entries for the DMACs Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs. Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g057-cpg.c | 24 ++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 3705e18f66ad..d63eafbca780 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -31,6 +31,8 @@ enum clk_ids { CLK_PLLVDO, /* Internal Core Clocks */ + CLK_PLLCM33_DIV4, + CLK_PLLCM33_DIV4_PLLCM33, CLK_PLLCM33_DIV16, CLK_PLLCLN_DIV2, CLK_PLLCLN_DIV8, @@ -39,6 +41,8 @@ enum clk_ids { CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_DIV16, + CLK_PLLDTY_RCPU, + CLK_PLLDTY_RCPU_DIV4, CLK_PLLVDO_CRU0, CLK_PLLVDO_CRU1, CLK_PLLVDO_CRU2, @@ -85,6 +89,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), + DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33, + CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), @@ -95,6 +102,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), + DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), @@ -115,6 +124,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { + DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0, + BUS_MSTOP(5, BIT(9))), + DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, + BUS_MSTOP(3, BIT(2))), + DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, + BUS_MSTOP(3, BIT(3))), + DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, + BUS_MSTOP(10, BIT(11))), + DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, + BUS_MSTOP(10, BIT(12))), DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, @@ -223,6 +242,11 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ + DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ + DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ + DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ + DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index fd8eb985c75b..576a070763cb 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -38,11 +38,13 @@ struct ddiv { #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) +#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14) #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) From 6c6ae70afb9a677a2dd9df72312d7df804815b6f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Feb 2025 09:44:45 +0100 Subject: [PATCH 2/6] clk: renesas: cpg-mssr: Remove obsolete nullify check All core clock nullify users and helpers were removed in commit b1dec4e78599a2ce ("clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*"), but the CPG/MSSR driver still checks for nullified core clocks. Remove the obsolete check. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/59ef3eccde0b0b63626480f27e77d5c68948ca98.1740126560.git.geert+renesas@glider.be --- drivers/clk/renesas/renesas-cpg-mssr.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index bf85501709f0..da021ee446ec 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -338,11 +338,6 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, WARN_DEBUG(id >= priv->num_core_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); - if (!core->name) { - /* Skip NULLified clock */ - return; - } - switch (core->type) { case CLK_TYPE_IN: clk = of_clk_get_by_name(priv->np, core->name); From 653395e63d53723f29b8cc1aa6bc4cbb873c7b7b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Feb 2025 09:44:46 +0100 Subject: [PATCH 3/6] clk: renesas: rzg2l: Remove unneeded nullify checks RZ/G2L family clock drivers never had a need to nullify clocks. Remove the unneeded checks. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/64702c33396dde2689b44d3e326aa1727ef1557a.1740126560.git.geert+renesas@glider.be --- drivers/clk/renesas/rzg2l-cpg.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index a6b87cc66cbb..b91dfbfb01e3 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1116,11 +1116,6 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, WARN_DEBUG(id >= priv->num_core_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); - if (!core->name) { - /* Skip NULLified clock */ - return; - } - switch (core->type) { case CLK_TYPE_IN: clk = of_clk_get_by_name(priv->dev->of_node, core->name); @@ -1355,11 +1350,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); - if (!mod->name) { - /* Skip NULLified clock */ - return; - } - parent = priv->clks[mod->parent]; if (IS_ERR(parent)) { clk = parent; From 5288fe0e2e9d2c147e18c5ce4d03d17f34132dde Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Feb 2025 09:44:47 +0100 Subject: [PATCH 4/6] clk: renesas: r7s9210: Distinguish clocks by clock type When registering a clock, its type should be devised from the clock's type member, not from its id member. Merge the two checks for the main clock, to improve readability. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/7e61ea78e9919148e73867088ccbc3509364952e.1740126560.git.geert+renesas@glider.be --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index a85227c248f3..e1812867a6da 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -170,11 +170,12 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, if (IS_ERR(parent)) return ERR_CAST(parent); - switch (core->id) { - case CLK_MAIN: + switch (core->type) { + case CLK_TYPE_RZA_MAIN: + r7s9210_update_clk_table(parent, base); break; - case CLK_PLL: + case CLK_TYPE_RZA_PLL: if (cpg_mode) mult = 44; /* Divider 1 is 1/2 */ else @@ -185,9 +186,6 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, return ERR_PTR(-EINVAL); } - if (core->id == CLK_MAIN) - r7s9210_update_clk_table(parent, base); - return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div); } From 69ac2acd209a15bd7a61a15c9532a5b505252e1c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 22 Feb 2025 14:20:07 +0000 Subject: [PATCH 5/6] clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 Avoid using the "- 1" for finding mstop_index in all functions accessing priv->mstop_count, by adjusting its pointer in rzv2h_cpg_probe(). While at it, drop the intermediate local variable index. Reported-by: Geert Uytterhoeven Closes: https://lore.kernel.org/all/CAMuHMdX1gPNCFddg_DyK7Bv0BeFLOLi=5eteT_HhMH=Ph2wVvA@mail.gmail.com/ Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250222142009.41324-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzv2h-cpg.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 419dc8cd2766..2b9771ab2b3f 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -447,8 +447,7 @@ static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); - unsigned int index = (mstop_index - 1) * 16; - atomic_t *mstop = &priv->mstop_count[index]; + atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; unsigned long flags; unsigned int i; u32 val = 0; @@ -469,8 +468,7 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv, { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); - unsigned int index = (mstop_index - 1) * 16; - atomic_t *mstop = &priv->mstop_count[index]; + atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; unsigned long flags; unsigned int i; u32 val = 0; @@ -630,8 +628,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data); u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data); - unsigned int index = (mstop_index - 1) * 16; - atomic_t *mstop = &priv->mstop_count[index]; + atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; unsigned long flags; unsigned int i; u32 val = 0; @@ -926,6 +923,9 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) if (!priv->mstop_count) return -ENOMEM; + /* Adjust for CPG_BUS_m_MSTOP starting from m = 1 */ + priv->mstop_count -= 16; + priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) * info->num_resets, GFP_KERNEL); if (!priv->resets) From e1a098330ef0555ad216e549a018d99aee7752c1 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Thu, 27 Feb 2025 13:24:38 +0100 Subject: [PATCH 6/6] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g047-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index ff015b3b4d2f..e9cf4342d0cf 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -183,6 +183,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(9, BIT(4))), DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, BUS_MSTOP(9, BIT(4))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@ -211,6 +213,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {