From 1e5e929c009559bd7e898ac8e17a5d01037cb057 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 25 Sep 2019 15:12:29 +0100 Subject: [PATCH 01/25] arm64: tegra: Fix 'active-low' warning for Jetson TX1 regulator Commit 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") added a regulator for HDMI on the Jetson TX1 platform. This regulator has an active high enable, but the GPIO specifier for enabling the regulator incorrectly defines it as active-low. This causes the following warning to occur on boot ... WARNING KERN regulator@10 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier which aligns with the presense of the 'enable-active-high' property. Fixes: 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a7dc319214a4..b0095072bc28 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1612,7 +1612,7 @@ vdd_hdmi: regulator@10 { regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&exp1 12 GPIO_ACTIVE_LOW>; + gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_5v0_sys>; }; From d440538e5f219900a9fc9d96fd10727b4d2b3c48 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 25 Sep 2019 15:12:28 +0100 Subject: [PATCH 02/25] arm64: tegra: Fix 'active-low' warning for Jetson Xavier regulator Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") added regulators for the PCIe slot on the Jetson Xavier platform. One of these regulators has an active-low enable and this commit incorrectly added an active-low specifier for the GPIO which causes the following warning to occur on boot ... WARNING KERN regulator@3 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier. Finally, remove the 'enable-active-low' as this is not a valid property. Fixes: 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 4c38426a6969..02909a48dfcd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -309,9 +309,8 @@ vdd_12v_pcie: regulator@3 { regulator-name = "VDD_12V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; regulator-boot-on; - enable-active-low; }; }; }; From b45d322c2cd5716176db22800a94a8139de42b95 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Sep 2019 16:56:21 +0200 Subject: [PATCH 03/25] arm64: tegra: Add CPU and cache topology for Tegra194 Tegra194 has four CPU clusters, each with their own cache hierarchy. This patch creates the CPU map for these clusters and adds the second- and third-level caches and associates them with the CPUs. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 156 +++++++++++++++++++++-- 1 file changed, 144 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3c0cf54f0aab..e02d975fe082 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1478,60 +1478,192 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0_0: cpu@0 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; - reg = <0x10000>; + reg = <0x000>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_0>; }; - cpu@1 { + cpu0_1: cpu@1 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; - reg = <0x10001>; + reg = <0x001>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_0>; }; - cpu@2 { + cpu1_0: cpu@100 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_1>; }; - cpu@3 { + cpu1_1: cpu@101 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x101>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_1>; }; - cpu@4 { + cpu2_0: cpu@200 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_2>; }; - cpu@5 { + cpu2_1: cpu@201 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x201>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_2>; }; - cpu@6 { + cpu3_0: cpu@300 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; - reg = <0x10300>; + reg = <0x300>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_3>; }; - cpu@7 { + cpu3_1: cpu@301 { compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; - reg = <0x10301>; + reg = <0x301>; enable-method = "psci"; + i-cache-size = <131072>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c_3>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0_0>; + }; + + core1 { + cpu = <&cpu0_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1_0>; + }; + + core1 { + cpu = <&cpu1_1>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2_0>; + }; + + core1 { + cpu = <&cpu2_1>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu3_0>; + }; + + core1 { + cpu = <&cpu3_1>; + }; + }; + }; + + l2c_0: l2-cache0 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + next-level-cache = <&l3c>; + }; + + l2c_1: l2-cache1 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + next-level-cache = <&l3c>; + }; + + l2c_2: l2-cache2 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + next-level-cache = <&l3c>; + }; + + l2c_3: l2-cache3 { + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + next-level-cache = <&l3c>; + }; + + l3c: l3-cache { + cache-size = <4194304>; + cache-line-size = <64>; + cache-sets = <4096>; }; }; From eef97c2a77febcccd3a9d70b9a6856ad43c7c069 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 26 Jul 2019 12:16:16 +0200 Subject: [PATCH 04/25] arm64: tegra: Add unit-address for CBB on Tegra194 The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 20 +++++++++---------- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 02909a48dfcd..56c0eb0e5b15 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -8,17 +8,17 @@ / { compatible = "nvidia,p2888", "nvidia,tegra194"; aliases { - sdhci0 = "/cbb/sdhci@3460000"; - sdhci1 = "/cbb/sdhci@3400000"; + sdhci0 = "/cbb@0/sdhci@3460000"; + sdhci1 = "/cbb@0/sdhci@3400000"; serial0 = &tcu; i2c0 = "/bpmp/i2c"; - i2c1 = "/cbb/i2c@3160000"; - i2c2 = "/cbb/i2c@c240000"; - i2c3 = "/cbb/i2c@3180000"; - i2c4 = "/cbb/i2c@3190000"; - i2c5 = "/cbb/i2c@31c0000"; - i2c6 = "/cbb/i2c@c250000"; - i2c7 = "/cbb/i2c@31e0000"; + i2c1 = "/cbb@0/i2c@3160000"; + i2c2 = "/cbb@0/i2c@c240000"; + i2c3 = "/cbb@0/i2c@3180000"; + i2c4 = "/cbb@0/i2c@3190000"; + i2c5 = "/cbb@0/i2c@31c0000"; + i2c6 = "/cbb@0/i2c@c250000"; + i2c7 = "/cbb@0/i2c@31e0000"; }; chosen { @@ -26,7 +26,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - cbb { + cbb@0 { ethernet@2490000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index d47cd8c4dd24..ae6094a60cc5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -10,7 +10,7 @@ / { model = "NVIDIA Jetson AGX Xavier Developer Kit"; compatible = "nvidia,p2972-0000", "nvidia,tegra194"; - cbb { + cbb@0 { aconnect { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index e02d975fe082..33743631e983 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -15,7 +15,7 @@ / { #size-cells = <2>; /* control backbone */ - cbb { + cbb@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 1aaa7698670cb980280e034d76f1bc1ca193af43 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 26 Jul 2019 12:16:17 +0200 Subject: [PATCH 05/25] arm64: tegra: Add unit-address for ACONNECT on Tegra194 The ACONNECT complex starts at physical address 0x2900000, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index ae6094a60cc5..7ea6d44e1031 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -11,7 +11,7 @@ / { compatible = "nvidia,p2972-0000", "nvidia,tegra194"; cbb@0 { - aconnect { + aconnect@2900000 { status = "okay"; dma-controller@2930000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 33743631e983..d15c4f0bf499 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -60,7 +60,7 @@ ethernet@2490000 { snps,rxpbl = <8>; }; - aconnect { + aconnect@2900000 { compatible = "nvidia,tegra194-aconnect", "nvidia,tegra210-aconnect"; clocks = <&bpmp TEGRA194_CLK_APE>, From 939e7430dee4e1c0595124b8ccd1c8b5db162dd8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 26 Jul 2019 12:16:18 +0200 Subject: [PATCH 06/25] arm64: tegra: Fix base address for SOR1 on Tegra194 The SOR1 hardware block's registers start at physical address 0x15b40000 as correctly specified by the unit-address, but the reg property lists a wrong value, likely because it was copy-and-pasted from SOR0 but not correctly updated. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d15c4f0bf499..a84a8b4dd598 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1078,7 +1078,7 @@ sor0: sor@15b00000 { sor1: sor@15b40000 { compatible = "nvidia,tegra194-sor"; - reg = <0x155c0000 0x40000>; + reg = <0x15b40000 0x40000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, <&bpmp TEGRA194_CLK_SOR1_OUT>, From 44ff822c58a7af0f458533e587283c05583da706 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 29 Aug 2019 12:56:47 +0200 Subject: [PATCH 07/25] arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 659753118e96..d21cf2758d27 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1457,7 +1457,9 @@ soctherm: thermal-sensor@700e2000 { reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ reg-names = "soctherm-reg", "car-reg"; - interrupts = ; + interrupts = , + ; + interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, <&tegra_car TEGRA210_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; From 19dc772a94bc92643210d5cba7d3477644b3032d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 25 Sep 2019 13:38:51 +0200 Subject: [PATCH 08/25] arm64: tegra: Fix compatible string for EQOS on Tegra194 The EQOS Ethernet controller found on Tegra194 is compatible with its predecessor or Tegra186. However, it is an established practice to add a compatible string for the most recent generation of the SoC as well, just in case some incompatibilities or bugs are later discovered. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a84a8b4dd598..a312c051448b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -39,7 +39,8 @@ gpio: gpio@2200000 { }; ethernet@2490000 { - compatible = "nvidia,tegra186-eqos", + compatible = "nvidia,tegra194-eqos", + "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; reg = <0x02490000 0x10000>; interrupts = ; From 2b6b3940e8b0968f7016aa5ff6db5b09ecf6ed1f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 1 Oct 2019 16:06:12 +0200 Subject: [PATCH 09/25] arm64: tegra: Add ethernet alias on Jetson AGX Xavier The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that. Generic bootloader code can use this to find the primary Ethernet device and set the MAC address, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 56c0eb0e5b15..1f8ea913853f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -8,6 +8,7 @@ / { compatible = "nvidia,p2888", "nvidia,tegra194"; aliases { + ethernet0 = "/cbb@0/ethernet@2490000"; sdhci0 = "/cbb@0/sdhci@3460000"; sdhci1 = "/cbb@0/sdhci@3400000"; serial0 = &tcu; From ca2b8ee4572141cbf5ad838dc732e49775f4913a Mon Sep 17 00:00:00 2001 From: Nagarjuna Kristam Date: Tue, 17 Sep 2019 12:26:43 +0530 Subject: [PATCH 10/25] arm64: tegra: Enable XUSB pad controller on Jetson TX2 The XUSB pad controller is a prerequisite for enabling XUSB support. Signed-off-by: Nagarjuna Kristam Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index bdace01561ba..b6503345f48e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -115,7 +115,7 @@ hda@3510000 { }; padctl@3520000 { - status = "disabled"; + status = "okay"; avdd-pll-erefeut-supply = <&vdd_1v8_pll>; avdd-usb-supply = <&vdd_3v3_sys>; From 05705c721591d0f8bdd1ea126f5d16176607c415 Mon Sep 17 00:00:00 2001 From: Nagarjuna Kristam Date: Tue, 17 Sep 2019 12:26:44 +0530 Subject: [PATCH 11/25] arm64: tegra: Enable SMMU for XUSB host on Tegra186 Enabling the SMMU for XUSB host allows buffers to be mapped through the ARM SMMU, which helps protecting the system from rogue memory accesses by the XUSB host. Signed-off-by: Nagarjuna Kristam Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 47cd831fcf44..abdc81f555b9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -525,6 +525,7 @@ usb@3530000 { <0x0 0x03538000 0x0 0x1000>; reg-names = "hcd", "fpci"; + iommus = <&smmu TEGRA186_SID_XUSB_HOST>; interrupts = , , ; From 488a04d4bb2f5d6216a982d8a390a218e405790c Mon Sep 17 00:00:00 2001 From: Nagarjuna Kristam Date: Tue, 17 Sep 2019 12:26:45 +0530 Subject: [PATCH 12/25] arm64: tegra: Enable XUSB host controller on Jetson TX2 This enables the use of the USB ports found on the Jetson TX2 for input or external storage, for example. Signed-off-by: Nagarjuna Kristam Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index b6503345f48e..2e6195764268 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -193,7 +193,7 @@ usb3-0 { }; usb@3530000 { - status = "disabled"; + status = "okay"; phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, From 29ef1f4dacb5ded606546a0cc1d448920c6f821a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 24 Jan 2019 19:02:54 +0100 Subject: [PATCH 13/25] arm64: tegra: Enable SMMU for VIC on Tegra186 Enable address translation for VIC via the SMMU on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index abdc81f555b9..1aea298c2165 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1019,6 +1019,7 @@ vic@15340000 { reset-names = "vic"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; + iommus = <&smmu TEGRA186_SID_VIC>; }; dsib: dsi@15400000 { From b7450f161f8ab91abeafaadafe05517a6ffbb26c Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Sat, 5 Oct 2019 22:12:12 +0530 Subject: [PATCH 14/25] arm64: tegra: Assume no CLKREQ presence by default Although Tegra194 has support for CLKREQ sideband signal and P2972 has routing of the same till the slot, it is the case most of the time that the connected device doesn't have CLKREQ support. Hence, it makes sense to assume that there is no CLKREQ support by default and it can be enabled on need basis when a card with CLKREQ support is connected. Signed-off-by: Vidya Sagar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a312c051448b..11220d97adb8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1186,7 +1186,6 @@ pcie@14100000 { nvidia,bpmp = <&bpmp 1>; - supports-clkreq; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; @@ -1232,7 +1231,6 @@ pcie@14120000 { nvidia,bpmp = <&bpmp 2>; - supports-clkreq; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; @@ -1278,7 +1276,6 @@ pcie@14140000 { nvidia,bpmp = <&bpmp 3>; - supports-clkreq; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; @@ -1324,7 +1321,6 @@ pcie@14160000 { nvidia,bpmp = <&bpmp 4>; - supports-clkreq; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; @@ -1370,7 +1366,6 @@ pcie@14180000 { nvidia,bpmp = <&bpmp 0>; - supports-clkreq; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; @@ -1420,7 +1415,6 @@ pcie@141a0000 { interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - supports-clkreq; nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; From ed93a666bb32cb35a0f4c42bf9f63a047a90d475 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Jun 2019 10:59:19 +0200 Subject: [PATCH 15/25] arm64: tegra: Add SOR0_OUT clock on Tegra210 This clock was not previously used because it is a fixed clock. However, adding it here allows operating systems to deal with SOR0 the same way as SOR1. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d21cf2758d27..a20cd368a772 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -254,10 +254,11 @@ sor@54540000 { reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_SOR0_OUT>, <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, <&tegra_car TEGRA210_CLK_PLL_DP>, <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; pinctrl-0 = <&state_dpaux_aux>; From 35cbf655eb16189b249c53c96378399cccfc3618 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 24 Jun 2019 15:57:07 +0200 Subject: [PATCH 16/25] arm64: tegra: Enable DP support on Jetson Nano Add the AVDD_IO_EDP_1V05 and enable the SOR and DPAUX hardware blocks that are used to drive DisplayPort on Jetson Nano. Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9d17ec707bce..eab2b12f0676 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -64,6 +64,16 @@ dpaux@54040000 { status = "okay"; }; + sor@54540000 { + status = "okay"; + + avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8>; + + nvidia,xbar-cfg = <2 1 0 3 4>; + nvidia,dpaux = <&dpaux>; + }; + sor@54580000 { status = "okay"; @@ -76,6 +86,10 @@ sor@54580000 { GPIO_ACTIVE_LOW>; nvidia,xbar-cfg = <0 1 2 3 4>; }; + + dpaux@545c0000 { + status = "okay"; + }; }; gpu@57000000 { @@ -680,5 +694,19 @@ vdd_gpu: regulator@6 { enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; vin-supply = <&vdd_5v0_sys>; }; + + avdd_io_edp_1v05: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + + regulator-name = "AVDD_IO_EDP_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&avdd_1v05_pll>; + }; }; }; From d46d1eb30c856798b62d27f86fa2973d707361c8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 19 Mar 2018 10:29:36 +0100 Subject: [PATCH 17/25] arm64: tegra: Fix compatible for SOR1 It turns out that both SORs on Tegra186 are the same, so there's no need to distinguish between them in the compatible string. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 1aea298c2165..7893d78a0fb6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1062,7 +1062,7 @@ sor0: sor@15540000 { }; sor1: sor@15580000 { - compatible = "nvidia,tegra186-sor1"; + compatible = "nvidia,tegra186-sor"; reg = <0x15580000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA186_CLK_SOR1>, From 3fdfaf8718fa9b806edb9f282b64d801f9866cf9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 1 Feb 2018 17:19:09 +0100 Subject: [PATCH 18/25] arm64: tegra: Enable DP support on Jetson TX2 If equipped with an E3320 display module, Jetson TX2 can support DisplayPort. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 2e6195764268..f1de4ff6230a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -253,10 +253,14 @@ dsi@15300000 { status = "disabled"; }; + /* DP on E3320 */ sor@15540000 { - status = "disabled"; + status = "okay"; - nvidia,dpaux = <&dpaux1>; + avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; + vdd-hdmi-dp-pll = <&vdd_1v8_ap>; + + nvidia,dpaux = <&dpaux>; }; sor@15580000 { From c90b8f15df41db52d604c8c2446e90ed90f20525 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 27 Jun 2019 12:22:26 +0200 Subject: [PATCH 19/25] arm64: tegra: p2888: Rename regulators for consistency Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the hardware documentation. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 1f8ea913853f..c7f2a20e6b02 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -169,7 +169,7 @@ regulators { in-ldo7-8-supply = <&vdd_1v8ls>; vdd_1v0: sd0 { - regulator-name = "VDD_1V0"; + regulator-name = "VDDIO_SYS_1V0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -177,7 +177,7 @@ vdd_1v0: sd0 { }; vdd_1v8hs: sd1 { - regulator-name = "VDD_1V8HS"; + regulator-name = "VDDIO_SYS_1V8HS"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -185,7 +185,7 @@ vdd_1v8hs: sd1 { }; vdd_1v8ls: sd2 { - regulator-name = "VDD_1V8LS"; + regulator-name = "VDDIO_SYS_1V8LS"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -193,7 +193,7 @@ vdd_1v8ls: sd2 { }; vdd_1v8ao: sd3 { - regulator-name = "VDD_1V8AO"; + regulator-name = "VDDIO_AO_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -217,7 +217,7 @@ ldo0 { }; ldo2 { - regulator-name = "VDD_AO_3V3"; + regulator-name = "VDDIO_AO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -243,7 +243,7 @@ ldo6 { }; ldo7 { - regulator-name = "VDD_CSI_1V2"; + regulator-name = "AVDD_CSI_1V2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; From 614d063f89b437b4a6db0c785573ca15b696c879 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 27 Jun 2019 12:23:45 +0200 Subject: [PATCH 20/25] arm64: tegra: Enable DisplayPort on Jetson AGX Xavier Enable both USB-C/DP ports on Jetson AGX Xavier and wire up the power supplies for the SORs that drive these outputs. Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 7ea6d44e1031..353a6a22196d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -46,10 +46,39 @@ display-hub@15200000 { status = "okay"; }; + dpaux@155c0000 { + status = "okay"; + }; + + dpaux@155d0000 { + status = "okay"; + }; + dpaux@155e0000 { status = "okay"; }; + /* DP0 */ + sor@15b00000 { + status = "okay"; + + avdd-io-hdmi-dp-supply = <&vdd_1v0>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; + + nvidia,dpaux = <&dpaux0>; + }; + + /* DP1 */ + sor@15b40000 { + status = "okay"; + + avdd-io-hdmi-dp-supply = <&vdd_1v0>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; + + nvidia,dpaux = <&dpaux1>; + }; + + /* HDMI */ sor@15b80000 { status = "okay"; From 24fc33633ea327f7887046bc9537a2ce8cddac53 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 29 Oct 2019 12:20:00 +0100 Subject: [PATCH 21/25] arm64: tegra: Add blank lines for better readability Separate the individual thermal zones by a blank line for improved readability. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a20cd368a772..aac7f3efee16 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1507,6 +1507,7 @@ map0 { }; }; }; + mem { polling-delay-passive = <0>; polling-delay = <0>; @@ -1529,6 +1530,7 @@ cooling-maps { */ }; }; + gpu { polling-delay-passive = <1000>; polling-delay = <0>; @@ -1557,6 +1559,7 @@ map0 { }; }; }; + pllx { polling-delay-passive = <0>; polling-delay = <0>; From 264064ab0b5cf30a1faf06696acc174e224e64a9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 29 Oct 2019 12:25:45 +0100 Subject: [PATCH 22/25] arm64: tegra: Add PMU on Tegra210 The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather statistics about the processors and their memory system. Add a device tree node so that this functionality can be exposed. Reported-by: William Cohen Tested-by: William Cohen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index aac7f3efee16..7832a3ea79c8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1439,6 +1439,16 @@ L2: l2-cache { }; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} + &{/cpus/cpu@2} &{/cpus/cpu@3}>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Fri, 16 Aug 2019 12:42:03 -0700 Subject: [PATCH 23/25] arm64: tegra: Enable wake from deep sleep on RTC alarm This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 7832a3ea79c8..48c63256ba7f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -769,7 +769,8 @@ spi@7000da00 { rtc@7000e000 { compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; @@ -779,6 +780,8 @@ pmc: pmc@7000e400 { reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #interrupt-cells = <2>; + interrupt-controller; powergates { pd_audio: aud { From 106f7a06fbe4f28db183d4c6b57b5fd60f6bdc4f Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Fri, 16 Aug 2019 12:42:06 -0700 Subject: [PATCH 24/25] arm64: tegra: Add Jetson TX1 SC7 timings Add platform specific SC7 timing configuration to the Jetson TX1 device tree. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 27723829d033..cb58f79deb48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -279,6 +279,13 @@ eeprom@50 { pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; /* eMMC */ From 47b4e129155fd1e721462fa23d128940c93b5b7b Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Fri, 16 Aug 2019 12:42:07 -0700 Subject: [PATCH 25/25] arm64: tegra: Add Jetson Nano SC7 timings Add platform specific SC7 timing configuration to the Jetson Nano device tree. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index eab2b12f0676..90381d52ac54 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -396,6 +396,13 @@ avdd_1v05: ldo8 { pmc@7000e400 { nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; hda@70030000 {