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firmware: xilinx: Add pinctrl support

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Adding pinctrl support to query platform specific information (pins)
from firmware.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/1619080202-31924-2-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Sai Krishna Potthuri
2021-04-22 14:00:00 +05:30
committed by Linus Walleij
parent fe202ea8e5
commit fa989ae7c7
2 changed files with 204 additions and 0 deletions
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90
include/linux/firmware/xlnx-zynqmp.h
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@@ -72,6 +72,12 @@ enum pm_api_id {
PM_FPGA_LOAD = 22,
PM_FPGA_GET_STATUS = 23,
PM_GET_CHIPID = 24,
PM_PINCTRL_REQUEST = 28,
PM_PINCTRL_RELEASE = 29,
PM_PINCTRL_GET_FUNCTION = 30,
PM_PINCTRL_SET_FUNCTION = 31,
PM_PINCTRL_CONFIG_PARAM_GET = 32,
PM_PINCTRL_CONFIG_PARAM_SET = 33,
PM_IOCTL = 34,
PM_QUERY_DATA = 35,
PM_CLOCK_ENABLE = 36,
@@ -122,6 +128,12 @@ enum pm_query_id {
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
PM_QID_CLOCK_GET_PARENTS = 4,
PM_QID_CLOCK_GET_ATTRIBUTES = 5,
PM_QID_PINCTRL_GET_NUM_PINS = 6,
PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
};
@@ -285,6 +297,44 @@ enum dll_reset_type {
PM_DLL_RESET_PULSE = 2,
};
enum pm_pinctrl_config_param {
PM_PINCTRL_CONFIG_SLEW_RATE = 0,
PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
PM_PINCTRL_CONFIG_PULL_CTRL = 2,
PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
PM_PINCTRL_CONFIG_TRI_STATE = 6,
PM_PINCTRL_CONFIG_MAX = 7,
};
enum pm_pinctrl_slew_rate {
PM_PINCTRL_SLEW_RATE_FAST = 0,
PM_PINCTRL_SLEW_RATE_SLOW = 1,
};
enum pm_pinctrl_bias_status {
PM_PINCTRL_BIAS_DISABLE = 0,
PM_PINCTRL_BIAS_ENABLE = 1,
};
enum pm_pinctrl_pull_ctrl {
PM_PINCTRL_BIAS_PULL_DOWN = 0,
PM_PINCTRL_BIAS_PULL_UP = 1,
};
enum pm_pinctrl_schmitt_cmos {
PM_PINCTRL_INPUT_TYPE_CMOS = 0,
PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
};
enum pm_pinctrl_drive_strength {
PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
};
enum zynqmp_pm_shutdown_type {
ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
@@ -353,6 +403,14 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
int zynqmp_pm_pinctrl_request(const u32 pin);
int zynqmp_pm_pinctrl_release(const u32 pin);
int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
u32 *value);
int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
u32 value);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -537,6 +595,38 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value)
{
return -ENODEV;
}
static inline int zynqmp_pm_pinctrl_request(const u32 pin)
{
return -ENODEV;
}
static inline int zynqmp_pm_pinctrl_release(const u32 pin)
{
return -ENODEV;
}
static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
{
return -ENODEV;
}
static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
{
return -ENODEV;
}
static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
u32 *value)
{
return -ENODEV;
}
static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
u32 value)
{
return -ENODEV;
}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */