From 61e137ce2cfe2c7bba9e24686dfe495cd6ce6ed8 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:54:08 +0200 Subject: [PATCH 01/38] ARM: dts: r7s72100: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 52a7b586bac7..b0db621ff176 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -57,7 +57,7 @@ &i2c2 { clock-frequency = <400000>; eeprom@50 { - compatible = "renesas,24c128"; + compatible = "renesas,24c128", "atmel,24c128"; reg = <0x50>; pagesize = <64>; }; From 3e82be14a1dcdfef75b5a87a25862bd7d878b7f8 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:54:09 +0200 Subject: [PATCH 02/38] ARM: dts: koelsch: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 001e6116c47c..dc8ed02de707 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -702,7 +702,7 @@ adv7612_out: endpoint { }; eeprom@50 { - compatible = "renesas,24c02"; + compatible = "renesas,24c02", "atmel,24c02"; reg = <0x50>; pagesize = <16>; }; From 328968b60231e522ea7e81ae0c83f59f13626a85 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 20 Apr 2017 21:51:33 +0300 Subject: [PATCH 03/38] ARM: dts: r8a7743: add PFC support Define the generic R8A7743 part of the PFC device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 0ddac81742e4..8d6b14075865 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7743 SoC * - * Copyright (C) 2016 Cogent Embedded Inc. + * Copyright (C) 2016-2017 Cogent Embedded Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -123,6 +123,11 @@ sysc: system-controller@e6180000 { #power-domain-cells = <1>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7743"; + reg = <0 0xe6060000 0 0x250>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7743", "renesas,rcar-dmac"; From 403812e4c4d853548237417fca2cf400351b72e6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 20 Apr 2017 21:51:34 +0300 Subject: [PATCH 04/38] ARM: dts: sk-rzg1m: add SCIF0 pins Add the (previously omitted) SCIF0 pin data to the SK-RZG1M board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts index 3a22538208f2..97a066c22003 100644 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -1,7 +1,7 @@ /* * Device Tree Source for the SK-RZG1M board * - * Copyright (C) 2016 Cogent Embedded, Inc. + * Copyright (C) 2016-2017 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -39,7 +39,17 @@ &extal_clk { clock-frequency = <20000000>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; From 51982d8f4722d1bbc2dabd79d4a1acebb90f6357 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 20 Apr 2017 21:51:35 +0300 Subject: [PATCH 05/38] ARM: dts: sk-rzg1m: add Ether pins Add the (previously omitted) Ether/PHY pin data to the SK-RZG1M board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts index 97a066c22003..3d918d106593 100644 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -44,6 +44,16 @@ scif0_pins: scif0 { groups = "scif0_data_d"; function = "scif0"; }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq0"; + function = "intc"; + }; }; &scif0 { @@ -54,6 +64,9 @@ &scif0 { }; ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; renesas,ether-link-active-low; status = "okay"; From 16ffb25335d7e91cebae9c29252536ddbeac96fa Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 4 Jul 2017 17:18:15 +0100 Subject: [PATCH 06/38] ARM: dts: r8a7743: Add GPIO support Describe GPIO blocks in the R8A7743 device tree. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 120 +++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 8d6b14075865..838085946588 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -65,6 +65,126 @@ gic: interrupt-controller@f1001000 { resets = <&cpg 408>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7743", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 904>; + }; + irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7743", "renesas,irqc"; #interrupt-cells = <2>; From 7095f279c03a05cf9007001852b939236edc2897 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 5 Jul 2017 11:57:35 +0100 Subject: [PATCH 07/38] ARM: dts: iwg20d-q7: Add pinctl support for scif0 Adding pinctrl support for scif0 interface. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 9b54783cc2a5..497aec00cfac 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -20,6 +20,16 @@ aliases { }; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; From 278a1df198625dde663978266de549e8317267cf Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 7 Jul 2017 14:12:44 +0100 Subject: [PATCH 08/38] ARM: dts: r8a7743: Add Ethernet AVB support Add Ethernet AVB support for r8a7743 SoC. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 838085946588..0c73fa8047b9 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -605,6 +605,19 @@ ether: ethernet@ee700000 { #size-cells = <0>; status = "disabled"; }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7743", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; /* External root clock */ From 9e70afe39eeb33488f0d18131b023b92c1493db8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 7 Jul 2017 14:12:45 +0100 Subject: [PATCH 09/38] ARM: dts: iwg20d-q7: Add Ethernet AVB support Define the iWave RainboW-G20D-Qseven board dependent part of the Ethernet AVB device node. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 497aec00cfac..081af0192851 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -17,6 +17,7 @@ / { aliases { serial0 = &scif0; + ethernet0 = &avb; }; }; @@ -25,6 +26,11 @@ scif0_pins: scif0 { groups = "scif0_data_d"; function = "scif0"; }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; }; &scif0 { @@ -33,3 +39,18 @@ &scif0 { status = "okay"; }; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; From 06278baa1b08f2b2ae26d5b2394b779ed82f3dfa Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:12 +0200 Subject: [PATCH 10/38] ARM: dts: r8a7743: Add Inter Connect RAM RZ/G1M has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 0c73fa8047b9..2cdb9a7115af 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -593,6 +593,21 @@ hscif2: serial@e62d0000 { status = "disabled"; }; + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7743"; reg = <0 0xee700000 0 0x400>; From 825216b8160b53b83f405a1e7b6c647e4e99e25a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:13 +0200 Subject: [PATCH 11/38] ARM: dts: r8a7745: Add Inter Connect RAM RZ/G1E has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 2feb0084bb3b..88cf92bcd2f9 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -468,6 +468,21 @@ hscif2: serial@e62d0000 { status = "disabled"; }; + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7745"; reg = <0 0xee700000 0 0x400>; From c90715a3ba3b01ff9a10bbffeca791062f2e3173 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:14 +0200 Subject: [PATCH 12/38] ARM: dts: r8a7790: Add Inter Connect RAM R-Car H2 has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2805a8608d4b..4ee34995573c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -830,6 +830,16 @@ hscif1: serial@e62c8000 { status = "disabled"; }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7790"; reg = <0 0xee700000 0 0x400>; From 5ccce438b9a58b9b99c3f847f7a40f3f8e48907b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:15 +0200 Subject: [PATCH 13/38] ARM: dts: r8a7791: Add Inter Connect RAM R-Car M2-W has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index bd93f699ad84..f4748a9cb037 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -890,6 +890,16 @@ hscif2: serial@e62d0000 { status = "disabled"; }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7791"; reg = <0 0xee700000 0 0x400>; From e63a6a48fad04255275a29c72ce49b9065200f43 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:16 +0200 Subject: [PATCH 14/38] ARM: dts: r8a7792: Add Inter Connect RAM R-Car V2H has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 0efecb232ee5..136a86ac6497 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -465,6 +465,16 @@ hscif1: serial@e62c8000 { status = "disabled"; }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7792"; reg = <0 0xee100000 0 0x328>; From 89d534d96a41c123bf67e419f0d7f7fc02dbcd25 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:17 +0200 Subject: [PATCH 15/38] ARM: dts: r8a7793: Add Inter Connect RAM R-Car M2-N has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 13b980f27bbc..bc6a44272f55 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -848,6 +848,16 @@ hscif2: serial@e62d0000 { status = "disabled"; }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7793"; reg = <0 0xee700000 0 0x400>; From 709f8d26223ee4ed7d9c43d9f80c792b6ee18220 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:23:18 +0200 Subject: [PATCH 16/38] ARM: dts: r8a7794: Add Inter Connect RAM R-Car E2 has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7d9a81d970d8..78973cee7185 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -588,6 +588,16 @@ hscif2: serial@e62d0000 { status = "disabled"; }; + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + }; + ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7794"; reg = <0 0xee700000 0 0x400>; From 857892bfc55e0a3fd0916bdac30fd7c0d81195bd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:37 +0200 Subject: [PATCH 17/38] ARM: dts: r8a7743: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 2cdb9a7115af..0d021919755c 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -606,6 +606,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; ether: ethernet@ee700000 { From d2791b1c8f6b3d308cd1bf529558d10c10a771a9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:38 +0200 Subject: [PATCH 18/38] ARM: dts: r8a7745: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 88cf92bcd2f9..354534cdc588 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -481,6 +481,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; ether: ethernet@ee700000 { From e66938697e2931aa01fef35a096a1c0efa85622e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:39 +0200 Subject: [PATCH 19/38] ARM: dts: r8a7790: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 4ee34995573c..ff986df23b62 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -838,6 +838,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; ether: ethernet@ee700000 { From d7ff938254e5665c06006893cf5335d2367a4b6a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:40 +0200 Subject: [PATCH 20/38] ARM: dts: r8a7791: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f4748a9cb037..e135da440eed 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -898,6 +898,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; ether: ethernet@ee700000 { From a81597bff9fe4e675b061dc7a028895b01d7fdd4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:41 +0200 Subject: [PATCH 21/38] ARM: dts: r8a7792: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 136a86ac6497..2623f39bed2b 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -473,6 +473,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; sdhi0: sd@ee100000 { From cbbf5d6cd14fe1875031fd2f52980efb197ff36c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:42 +0200 Subject: [PATCH 22/38] ARM: dts: r8a7793: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index bc6a44272f55..497716b6fbe2 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -856,6 +856,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; ether: ethernet@ee700000 { From 18951ad1dccf76fc4f8956f7d3db0e242a4fa316 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Jul 2017 17:41:43 +0200 Subject: [PATCH 23/38] ARM: dts: r8a7794: Reserve SRAM for the SMP jump stub Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 78973cee7185..f32b458e9328 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -596,6 +596,14 @@ icram0: sram@e63a0000 { icram1: sram@e63c0000 { compatible = "mmio-sram"; reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x10>; + }; }; ether: ethernet@ee700000 { From 873038ddc34b62b55b2ad919995d3f70be12f192 Mon Sep 17 00:00:00 2001 From: Chris Paterson Date: Wed, 12 Jul 2017 11:03:24 +0100 Subject: [PATCH 24/38] ARM: dts: r8a7743: Add MMCIF0 support Add the MMCIF0 device to the r8a7743 device tree. Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 0d021919755c..f62e8587f1a8 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -641,6 +641,22 @@ avb: ethernet@e6800000 { #size-cells = <0>; status = "disabled"; }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7743", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; }; /* External root clock */ From a94b9e569c8e087c063fb0e66507681453a798b3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 11 Jul 2017 14:56:47 +0200 Subject: [PATCH 25/38] ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding for vin nodes Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7790 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7790 and the fallback binding for R-Car Gen 2 Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ff986df23b62..167fd57aea68 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -927,7 +927,7 @@ usb2: usb-channel@2 { }; vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790"; + compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7790_CLK_VIN0>; @@ -936,7 +936,7 @@ vin0: video@e6ef0000 { }; vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790"; + compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7790_CLK_VIN1>; @@ -945,7 +945,7 @@ vin1: video@e6ef1000 { }; vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790"; + compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7790_CLK_VIN2>; @@ -954,7 +954,7 @@ vin2: video@e6ef2000 { }; vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790"; + compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7790_CLK_VIN3>; From b5595f2ffec64cce76fd1c6e4bfeb7a0109517a7 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 11 Jul 2017 14:56:48 +0200 Subject: [PATCH 26/38] ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding for vin nodes Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7791 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7791 and the fallback binding for R-Car Gen 2 Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e135da440eed..ea4a8147d995 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -987,7 +987,7 @@ usb2: usb-channel@2 { }; vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791"; + compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7791_CLK_VIN0>; @@ -996,7 +996,7 @@ vin0: video@e6ef0000 { }; vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791"; + compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7791_CLK_VIN1>; @@ -1005,7 +1005,7 @@ vin1: video@e6ef1000 { }; vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791"; + compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7791_CLK_VIN2>; From a3fbb1dc134f65352ca9188bb23acb233d0b9d89 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 11 Jul 2017 14:56:49 +0200 Subject: [PATCH 27/38] ARM: dts: r8a7794: Use R-Car Gen 2 fallback binding for vin nodes Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7794 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7794 and the fallback binding for R-Car Gen 2 Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index f32b458e9328..26535414203a 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -801,7 +801,7 @@ qspi: spi@e6b10000 { }; vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794"; + compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7794_CLK_VIN0>; @@ -810,7 +810,7 @@ vin0: video@e6ef0000 { }; vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794"; + compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&mstp8_clks R8A7794_CLK_VIN1>; From a03633abae89b5ab9d99c95e6dbf7cf15e5a441e Mon Sep 17 00:00:00 2001 From: Chris Paterson Date: Thu, 13 Jul 2017 16:39:00 +0100 Subject: [PATCH 28/38] ARM: dts: iwg20m: Add MMCIF0 support Define the iwg20m board dependent part of the MMCIF0 device node. Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index 001ca9144f4b..f78dbc542a82 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -22,8 +22,34 @@ memory@200000000 { device_type = "memory"; reg = <2 0x00000000 0 0x20000000>; }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; }; &extal_clk { clock-frequency = <20000000>; }; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8_b", "mmc_ctrl"; + function = "mmc"; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; From 0d69caa69854b5e59f8079b835e55f725b9e3313 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 22 Jun 2017 16:54:32 +0200 Subject: [PATCH 29/38] ARM: dts: r7s72100: Add pin controller node Add pin controller node with 12 gpio controller sub-nodes to r7s72100 dtsi. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 78 +++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 5cf53e9943af..4ed12a4d9d51 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -207,6 +207,84 @@ cpu@0 { }; }; + pinctrl: pin-controller@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + port0: gpio-0 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 6>; + }; + + port1: gpio-1 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + port2: gpio-2 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + port4: gpio-4 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + port5: gpio-5 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 80 11>; + }; + + port6: gpio-6 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + port7: gpio-7 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + port8: gpio-8 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + port9: gpio-9 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 144 8>; + }; + + port10: gpio-10 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 160 16>; + }; + + port11: gpio-11 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 176 16>; + }; + }; + scif0: serial@e8007000 { compatible = "renesas,scif-r7s72100", "renesas,scif"; reg = <0xe8007000 64>; From 177f8744b960ce9a3a5a4086722bb468c01cdc66 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 22 Jun 2017 16:54:33 +0200 Subject: [PATCH 30/38] ARM: dts: genmai: Add SCIF2 pin group Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index b0db621ff176..12306ff18353 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r7s72100.dtsi" +#include / { model = "Genmai"; @@ -36,6 +37,14 @@ lbsc { }; }; +&pinctrl { + + scif2_pins: serial2 { + /* P3_0 as TxD2; P3_2 as RxD2 */ + pinmux = , ; + }; +}; + &extal_clk { clock-frequency = <13330000>; }; @@ -68,6 +77,9 @@ &rtc { }; &scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + status = "okay"; }; From 2d164e690f040c5bb58117ab35175ae585f53c58 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 22 Jun 2017 16:54:34 +0200 Subject: [PATCH 31/38] ARM: dts: genmai: Add RIIC2 pin group Add pin configuration subnode for RIIC2 interface. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 12306ff18353..0766661d4206 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -43,6 +43,11 @@ scif2_pins: serial2 { /* P3_0 as TxD2; P3_2 as RxD2 */ pinmux = , ; }; + + i2c2_pins: i2c2 { + /* RIIC2: P1_4 as SCL, P1_5 as SDA */ + pinmux = , ; + }; }; &extal_clk { @@ -65,6 +70,9 @@ &i2c2 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + eeprom@50 { compatible = "renesas,24c128", "atmel,24c128"; reg = <0x50>; From 55ec65552d3b53987853c61bd487de9e239f06a3 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 22 Jun 2017 16:54:35 +0200 Subject: [PATCH 32/38] ARM: dts: genmai: Add user led device nodes Add device nodes for user leds on Genmai board. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 0766661d4206..e7824f0857c6 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r7s72100.dtsi" +#include #include / { @@ -35,6 +36,19 @@ lbsc { #address-cells = <1>; #size-cells = <1>; }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port4 10 GPIO_ACTIVE_LOW>; + }; + + led2 { + gpios = <&port4 11 GPIO_ACTIVE_LOW>; + }; + }; }; &pinctrl { From 6f9a9720b0e6cf4760e0965bea74270d0b467ad2 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 22 Jun 2017 16:54:36 +0200 Subject: [PATCH 33/38] ARM: dts: genmai: Add ethernet pin group Add pin configuration subnode for ETHER ethernet controller. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index e7824f0857c6..cd4d5ff7749e 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -62,6 +62,28 @@ i2c2_pins: i2c2 { /* RIIC2: P1_4 as SCL, P1_5 as SDA */ pinmux = , ; }; + + ether_pins: ether { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = ,/* P1_14 = ET_COL */ + , /* P5_9 = ET_MDC */ + , /* P3_3 = ET_MDIO */ + , /* P3_4 = ET_RXCLK */ + , /* P3_5 = ET_RXER */ + , /* P3_6 = ET_RXDV */ + , /* P2_0 = ET_TXCLK */ + , /* P2_1 = ET_TXER */ + , /* P2_2 = ET_TXEN */ + , /* P2_3 = ET_CRS */ + , /* P2_4 = ET_TXD0 */ + , /* P2_5 = ET_TXD1 */ + , /* P2_6 = ET_TXD2 */ + , /* P2_7 = ET_TXD3 */ + , /* P2_8 = ET_RXD0 */ + , /* P2_9 = ET_RXD1 */ + ,/* P2_10 = ET_RXD2 */ + ;/* P2_11 = ET_RXD3 */ + }; }; &extal_clk { @@ -80,6 +102,19 @@ &mtu2 { status = "okay"; }; +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &i2c2 { status = "okay"; clock-frequency = <400000>; From cde2380548e26afe03e4c9310073e0878af9efd9 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 20 Jul 2017 13:20:16 -0500 Subject: [PATCH 34/38] ARM: dts: rskrza1: Add SCIF2 pin group Add pin configuration for SCIF2 serial console interface. Signed-off-by: Chris Brandt Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 72df20a04320..5fac0f82d742 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r7s72100.dtsi" +#include / { model = "RSKRZA1"; @@ -47,6 +48,15 @@ &rtc_x1_clk { clock-frequency = <32768>; }; +&pinctrl { + + /* Serial Console */ + scif2_pins: serial2 { + pinmux = , /* TxD2 */ + ; /* RxD2 */ + }; +}; + &mtu2 { status = "okay"; }; @@ -78,5 +88,7 @@ &rtc { }; &scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; status = "okay"; }; From 4cb674cd204dc95eeb6d1ea11735510ee6b02180 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 20 Jul 2017 13:20:17 -0500 Subject: [PATCH 35/38] ARM: dts: rskrza1: Add Ethernet pin group Add pin configuration for Ethernet. Signed-off-by: Chris Brandt Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 5fac0f82d742..cedf887e809a 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -55,6 +55,29 @@ scif2_pins: serial2 { pinmux = , /* TxD2 */ ; /* RxD2 */ }; + + /* Ethernet */ + ether_pins: ether { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = , /* ET_COL */ + , /* ET_MDC */ + , /* ET_MDIO */ + , /* ET_RXCLK */ + , /* ET_RXER */ + , /* ET_RXDV */ + , /* ET_TXCLK */ + , /* ET_TXER */ + , /* ET_TXEN */ + , /* ET_CRS */ + , /* ET_TXD0 */ + , /* ET_TXD1 */ + , /* ET_TXD2 */ + , /* ET_TXD3 */ + , /* ET_RXD0 */ + , /* ET_RXD1 */ + , /* ET_RXD2 */ + ; /* ET_RXD3 */ + }; }; &mtu2 { @@ -62,6 +85,8 @@ &mtu2 { }; ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; status = "okay"; renesas,no-ether-link; phy-handle = <&phy0>; From 35ff4c0edf7779c455cb41e727f59ed10e478416 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 20 Jul 2017 13:20:18 -0500 Subject: [PATCH 36/38] ARM: dts: rskrza1: Add SDHI1 pin group Add pin configuration for SDHI ch1. Signed-off-by: Chris Brandt Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index cedf887e809a..f8285b951140 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -78,6 +78,18 @@ ether_pins: ether { , /* ET_RXD2 */ ; /* ET_RXD3 */ }; + + /* SDHI ch1 on CN1 */ + sdhi1_pins: sdhi1 { + pinmux = , /* SD_CD_1 */ + , /* SD_WP_1 */ + , /* SD_D1_1 */ + , /* SD_D0_1 */ + , /* SD_CLK_1 */ + , /* SD_CMD_1 */ + , /* SD_D3_1 */ + ; /* SD_D2_1 */ + }; }; &mtu2 { @@ -96,6 +108,8 @@ phy0: ethernet-phy@0 { }; &sdhi1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; bus-width = <4>; status = "okay"; }; From a4604f4d245fe58aac3bc792296ef2e9ec774e12 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 20 Jul 2017 13:20:19 -0500 Subject: [PATCH 37/38] ARM: dts: rskrza1: Add LED0 pin support Add pin configuration for LED0 which is connected to a GPIO. Signed-off-by: Chris Brandt Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index f8285b951140..5dcaaf131d27 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r7s72100.dtsi" +#include #include / { @@ -34,6 +35,15 @@ lbsc { #address-cells = <1>; #size-cells = <1>; }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led0 { + gpios = <&port7 1 GPIO_ACTIVE_LOW>; + }; + }; }; &extal_clk { From bf38b9ac16c5c8a82d63c79391dd64c5924fc00b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 17 Jul 2017 14:06:37 +0200 Subject: [PATCH 38/38] ARM: dts: iwg20m: Correct indentation of mmcif0 properties Fixes: 4658c4b789d8e2ae ("ARM: dts: iwg20m: Add MMCIF0 support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index f78dbc542a82..ff7993818637 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -45,11 +45,11 @@ mmcif0_pins: mmc { }; &mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; };