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Merge tag 'v3.16-rc4' into drm-intel-next-queued

Browse Source 
Due to Dave's vacation drm-next hasn't opened yet for 3.17 so I
couldn't move my drm-intel-next queue forward yet like I usually do.
Just pull in the latest upstream -rc to unblock patch merging - I
don't want to needlessly rebase my current patch pile really and void
all the testing we've done already.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
2014-07-07 10:17:56 +02:00
parent cfb3c0ab09 cd3de83f14
commit f1615bbe9b
9054 changed files with 458338 additions and 234903 deletions
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10
include/acpi/processor.h
View File

@@ -53,7 +53,7 @@ struct acpi_power_register {
u8 bit_offset;
u8 access_size;
u64 address;
} __attribute__ ((packed));
} __packed;
struct acpi_processor_cx {
u8 valid;
@@ -83,7 +83,7 @@ struct acpi_psd_package {
u64 domain;
u64 coord_type;
u64 num_processors;
} __attribute__ ((packed));
} __packed;
struct acpi_pct_register {
u8 descriptor;
@@ -93,7 +93,7 @@ struct acpi_pct_register {
u8 bit_offset;
u8 reserved;
u64 address;
} __attribute__ ((packed));
} __packed;
struct acpi_processor_px {
u64 core_frequency; /* megahertz */
@@ -124,7 +124,7 @@ struct acpi_tsd_package {
u64 domain;
u64 coord_type;
u64 num_processors;
} __attribute__ ((packed));
} __packed;
struct acpi_ptc_register {
u8 descriptor;
@@ -134,7 +134,7 @@ struct acpi_ptc_register {
u8 bit_offset;
u8 reserved;
u64 address;
} __attribute__ ((packed));
} __packed;
struct acpi_processor_tx_tss {
u64 freqpercentage; /* */

7
include/asm-generic/atomic.h
View File

@@ -16,6 +16,7 @@
#define __ASM_GENERIC_ATOMIC_H
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
#ifdef CONFIG_SMP
/* Force people to define core atomics */
@@ -182,11 +183,5 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
}
#endif
/* Assume that atomic operations are already serializing */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#endif /* __KERNEL__ */
#endif /* __ASM_GENERIC_ATOMIC_H */

8
include/asm-generic/barrier.h
View File

@@ -62,6 +62,14 @@
#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
#endif
#ifndef smp_mb__before_atomic
#define smp_mb__before_atomic() smp_mb()
#endif
#ifndef smp_mb__after_atomic
#define smp_mb__after_atomic() smp_mb()
#endif
#define smp_store_release(p, v) \
do { \
compiletime_assert_atomic_type(*p); \

9
include/asm-generic/bitops.h
View File

@@ -11,14 +11,7 @@
#include <linux/irqflags.h>
#include <linux/compiler.h>
/*
* clear_bit may not imply a memory barrier
*/
#ifndef smp_mb__before_clear_bit
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
#endif
#include <asm/barrier.h>
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/ffz.h>

2
include/asm-generic/bitops/atomic.h
View File

@@ -80,7 +80,7 @@ static inline void set_bit(int nr, volatile unsigned long *addr)
*
* clear_bit() is atomic and may not be reordered. However, it does
* not contain a memory barrier, so if it is used for locking purposes,
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
* in order to ensure changes are visible on other processors.
*/
static inline void clear_bit(int nr, volatile unsigned long *addr)

2
include/asm-generic/bitops/lock.h
View File

@@ -20,7 +20,7 @@
*/
#define clear_bit_unlock(nr, addr) \
do { \
smp_mb__before_clear_bit(); \
smp_mb__before_atomic(); \
clear_bit(nr, addr); \
} while (0)

13
include/asm-generic/dma-coherent.h
View File

@@ -16,16 +16,13 @@ int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma,
* Standard interface
*/
#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
dma_addr_t device_addr, size_t size, int flags);
int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
dma_addr_t device_addr, size_t size, int flags);
extern void
dma_release_declared_memory(struct device *dev);
void dma_release_declared_memory(struct device *dev);
extern void *
dma_mark_declared_memory_occupied(struct device *dev,
dma_addr_t device_addr, size_t size);
void *dma_mark_declared_memory_occupied(struct device *dev,
dma_addr_t device_addr, size_t size);
#else
#define dma_alloc_from_coherent(dev, size, handle, ret) (0)
#define dma_release_from_coherent(dev, order, vaddr) (0)

5
include/asm-generic/ioctl.h
View File

@@ -3,10 +3,15 @@
#include <uapi/asm-generic/ioctl.h>
#ifdef __CHECKER__
#define _IOC_TYPECHECK(t) (sizeof(t))
#else
/* provoke compile error for invalid uses of size argument */
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) \
((sizeof(t) == sizeof(t[1]) && \
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
sizeof(t) : __invalid_size_argument_for_IOC)
#endif
#endif /* _ASM_GENERIC_IOCTL_H */

8
include/asm-generic/pgtable.h
View File

@@ -233,6 +233,10 @@ static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
# define pte_accessible(mm, pte) ((void)(pte), 1)
#endif
#ifndef pte_present_nonuma
#define pte_present_nonuma(pte) pte_present(pte)
#endif
#ifndef flush_tlb_fix_spurious_fault
#define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address)
#endif
@@ -670,7 +674,7 @@ static inline int pmd_trans_unstable(pmd_t *pmd)
static inline int pte_numa(pte_t pte)
{
return (pte_flags(pte) &
(_PAGE_NUMA|_PAGE_PRESENT)) == _PAGE_NUMA;
(_PAGE_NUMA|_PAGE_PROTNONE|_PAGE_PRESENT)) == _PAGE_NUMA;
}
#endif
@@ -678,7 +682,7 @@ static inline int pte_numa(pte_t pte)
static inline int pmd_numa(pmd_t pmd)
{
return (pmd_flags(pmd) &
(_PAGE_NUMA|_PAGE_PRESENT)) == _PAGE_NUMA;
(_PAGE_NUMA|_PAGE_PROTNONE|_PAGE_PRESENT)) == _PAGE_NUMA;
}
#endif

166
include/asm-generic/qrwlock.h Normal file
View File

@@ -0,0 +1,166 @@
/*
* Queue read/write lock
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* (C) Copyright 2013-2014 Hewlett-Packard Development Company, L.P.
*
* Authors: Waiman Long <waiman.long@hp.com>
*/
#ifndef __ASM_GENERIC_QRWLOCK_H
#define __ASM_GENERIC_QRWLOCK_H
#include <linux/atomic.h>
#include <asm/barrier.h>
#include <asm/processor.h>
#include <asm-generic/qrwlock_types.h>
/*
* Writer states & reader shift and bias
*/
#define _QW_WAITING 1 /* A writer is waiting */
#define _QW_LOCKED 0xff /* A writer holds the lock */
#define _QW_WMASK 0xff /* Writer mask */
#define _QR_SHIFT 8 /* Reader count shift */
#define _QR_BIAS (1U << _QR_SHIFT)
/*
* External function declarations
*/
extern void queue_read_lock_slowpath(struct qrwlock *lock);
extern void queue_write_lock_slowpath(struct qrwlock *lock);
/**
* queue_read_can_lock- would read_trylock() succeed?
* @lock: Pointer to queue rwlock structure
*/
static inline int queue_read_can_lock(struct qrwlock *lock)
{
return !(atomic_read(&lock->cnts) & _QW_WMASK);
}
/**
* queue_write_can_lock- would write_trylock() succeed?
* @lock: Pointer to queue rwlock structure
*/
static inline int queue_write_can_lock(struct qrwlock *lock)
{
return !atomic_read(&lock->cnts);
}
/**
* queue_read_trylock - try to acquire read lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* Return: 1 if lock acquired, 0 if failed
*/
static inline int queue_read_trylock(struct qrwlock *lock)
{
u32 cnts;
cnts = atomic_read(&lock->cnts);
if (likely(!(cnts & _QW_WMASK))) {
cnts = (u32)atomic_add_return(_QR_BIAS, &lock->cnts);
if (likely(!(cnts & _QW_WMASK)))
return 1;
atomic_sub(_QR_BIAS, &lock->cnts);
}
return 0;
}
/**
* queue_write_trylock - try to acquire write lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
* Return: 1 if lock acquired, 0 if failed
*/
static inline int queue_write_trylock(struct qrwlock *lock)
{
u32 cnts;
cnts = atomic_read(&lock->cnts);
if (unlikely(cnts))
return 0;
return likely(atomic_cmpxchg(&lock->cnts,
cnts, cnts | _QW_LOCKED) == cnts);
}
/**
* queue_read_lock - acquire read lock of a queue rwlock
* @lock: Pointer to queue rwlock structure
*/
static inline void queue_read_lock(struct qrwlock *lock)
{
u32 cnts;
cnts = atomic_add_return(_QR_BIAS, &lock->cnts);
if (likely(!(cnts & _QW_WMASK)))
return;
/* The slowpath will decrement the reader count, if necessary. */
queue_read_lock_slowpath(lock);
}
/**
* queue_write_lock - acquire write lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
*/
static inline void queue_write_lock(struct qrwlock *lock)
{
/* Optimize for the unfair lock case where the fair flag is 0. */
if (atomic_cmpxchg(&lock->cnts, 0, _QW_LOCKED) == 0)
return;
queue_write_lock_slowpath(lock);
}
/**
* queue_read_unlock - release read lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
*/
static inline void queue_read_unlock(struct qrwlock *lock)
{
/*
* Atomically decrement the reader count
*/
smp_mb__before_atomic();
atomic_sub(_QR_BIAS, &lock->cnts);
}
#ifndef queue_write_unlock
/**
* queue_write_unlock - release write lock of a queue rwlock
* @lock : Pointer to queue rwlock structure
*/
static inline void queue_write_unlock(struct qrwlock *lock)
{
/*
* If the writer field is atomic, it can be cleared directly.
* Otherwise, an atomic subtraction will be used to clear it.
*/
smp_mb__before_atomic();
atomic_sub(_QW_LOCKED, &lock->cnts);
}
#endif
/*
* Remapping rwlock architecture specific functions to the corresponding
* queue rwlock functions.
*/
#define arch_read_can_lock(l) queue_read_can_lock(l)
#define arch_write_can_lock(l) queue_write_can_lock(l)
#define arch_read_lock(l) queue_read_lock(l)
#define arch_write_lock(l) queue_write_lock(l)
#define arch_read_trylock(l) queue_read_trylock(l)
#define arch_write_trylock(l) queue_write_trylock(l)
#define arch_read_unlock(l) queue_read_unlock(l)
#define arch_write_unlock(l) queue_write_unlock(l)
#endif /* __ASM_GENERIC_QRWLOCK_H */

21
include/asm-generic/qrwlock_types.h Normal file
View File

@@ -0,0 +1,21 @@
#ifndef __ASM_GENERIC_QRWLOCK_TYPES_H
#define __ASM_GENERIC_QRWLOCK_TYPES_H
#include <linux/types.h>
#include <asm/spinlock_types.h>
/*
* The queue read/write lock data structure
*/
typedef struct qrwlock {
atomic_t cnts;
arch_spinlock_t lock;
} arch_rwlock_t;
#define __ARCH_RW_LOCK_UNLOCKED { \
.cnts = ATOMIC_INIT(0), \
.lock = __ARCH_SPIN_LOCK_UNLOCKED, \
}
#endif /* __ASM_GENERIC_QRWLOCK_TYPES_H */

21
include/asm-generic/unaligned.h
View File

@@ -4,22 +4,27 @@
/*
* This is the most generic implementation of unaligned accesses
* and should work almost anywhere.
*
* If an architecture can handle unaligned accesses in hardware,
* it may want to use the linux/unaligned/access_ok.h implementation
* instead.
*/
#include <asm/byteorder.h>
/* Set by the arch if it can handle unaligned accesses in hardware. */
#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
# include <linux/unaligned/access_ok.h>
#endif
#if defined(__LITTLE_ENDIAN)
# include <linux/unaligned/le_struct.h>
# include <linux/unaligned/be_byteshift.h>
# ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
# include <linux/unaligned/le_struct.h>
# include <linux/unaligned/be_byteshift.h>
# endif
# include <linux/unaligned/generic.h>
# define get_unaligned __get_unaligned_le
# define put_unaligned __put_unaligned_le
#elif defined(__BIG_ENDIAN)
# include <linux/unaligned/be_struct.h>
# include <linux/unaligned/le_byteshift.h>
# ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
# include <linux/unaligned/be_struct.h>
# include <linux/unaligned/le_byteshift.h>
# endif
# include <linux/unaligned/generic.h>
# define get_unaligned __get_unaligned_be
# define put_unaligned __put_unaligned_be

70
include/asm-generic/vmlinux.lds.h
View File

@@ -109,6 +109,15 @@
#define BRANCH_PROFILE()
#endif
#ifdef CONFIG_KPROBES
#define KPROBE_BLACKLIST() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \
*(_kprobe_blacklist) \
VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .;
#else
#define KPROBE_BLACKLIST()
#endif
#ifdef CONFIG_EVENT_TRACING
#define FTRACE_EVENTS() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_ftrace_events) = .; \
@@ -139,52 +148,23 @@
#define TRACE_SYSCALLS()
#endif
#ifdef CONFIG_CLKSRC_OF
#define CLKSRC_OF_TABLES() . = ALIGN(8); \
VMLINUX_SYMBOL(__clksrc_of_table) = .; \
*(__clksrc_of_table) \
*(__clksrc_of_table_end)
#else
#define CLKSRC_OF_TABLES()
#endif
#ifdef CONFIG_IRQCHIP
#define IRQCHIP_OF_MATCH_TABLE() \
#define ___OF_TABLE(cfg, name) _OF_TABLE_##cfg(name)
#define __OF_TABLE(cfg, name) ___OF_TABLE(cfg, name)
#define OF_TABLE(cfg, name) __OF_TABLE(config_enabled(cfg), name)
#define _OF_TABLE_0(name)
#define _OF_TABLE_1(name) \
. = ALIGN(8); \
VMLINUX_SYMBOL(__irqchip_begin) = .; \
*(__irqchip_of_table) \
*(__irqchip_of_end)
#else
#define IRQCHIP_OF_MATCH_TABLE()
#endif
VMLINUX_SYMBOL(__##name##_of_table) = .; \
*(__##name##_of_table) \
*(__##name##_of_table_end)
#ifdef CONFIG_COMMON_CLK
#define CLK_OF_TABLES() . = ALIGN(8); \
VMLINUX_SYMBOL(__clk_of_table) = .; \
*(__clk_of_table) \
*(__clk_of_table_end)
#else
#define CLK_OF_TABLES()
#endif
#ifdef CONFIG_OF_RESERVED_MEM
#define RESERVEDMEM_OF_TABLES() \
. = ALIGN(8); \
VMLINUX_SYMBOL(__reservedmem_of_table) = .; \
*(__reservedmem_of_table) \
*(__reservedmem_of_table_end)
#else
#define RESERVEDMEM_OF_TABLES()
#endif
#ifdef CONFIG_SMP
#define CPU_METHOD_OF_TABLES() . = ALIGN(8); \
VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
*(__cpu_method_of_table) \
VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
#else
#define CPU_METHOD_OF_TABLES()
#endif
#define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc)
#define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip)
#define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk)
#define RESERVEDMEM_OF_TABLES() OF_TABLE(CONFIG_OF_RESERVED_MEM, reservedmem)
#define CPU_METHOD_OF_TABLES() OF_TABLE(CONFIG_SMP, cpu_method)
#define EARLYCON_OF_TABLES() OF_TABLE(CONFIG_SERIAL_EARLYCON, earlycon)
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
@@ -507,13 +487,15 @@
*(.init.rodata) \
FTRACE_EVENTS() \
TRACE_SYSCALLS() \
KPROBE_BLACKLIST() \
MEM_DISCARD(init.rodata) \
CLK_OF_TABLES() \
RESERVEDMEM_OF_TABLES() \
CLKSRC_OF_TABLES() \
CPU_METHOD_OF_TABLES() \
KERNEL_DTB() \
IRQCHIP_OF_MATCH_TABLE()
IRQCHIP_OF_MATCH_TABLE() \
EARLYCON_OF_TABLES()
#define INIT_TEXT \
*(.init.text) \

13
include/crypto/internal/hash.h
View File

@@ -55,15 +55,28 @@ extern const struct crypto_type crypto_ahash_type;
int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err);
int crypto_hash_walk_first(struct ahash_request *req,
struct crypto_hash_walk *walk);
int crypto_ahash_walk_first(struct ahash_request *req,
struct crypto_hash_walk *walk);
int crypto_hash_walk_first_compat(struct hash_desc *hdesc,
struct crypto_hash_walk *walk,
struct scatterlist *sg, unsigned int len);
static inline int crypto_ahash_walk_done(struct crypto_hash_walk *walk,
int err)
{
return crypto_hash_walk_done(walk, err);
}
static inline int crypto_hash_walk_last(struct crypto_hash_walk *walk)
{
return !(walk->entrylen | walk->total);
}
static inline int crypto_ahash_walk_last(struct crypto_hash_walk *walk)
{
return crypto_hash_walk_last(walk);
}
int crypto_register_ahash(struct ahash_alg *alg);
int crypto_unregister_ahash(struct ahash_alg *alg);
int ahash_register_instance(struct crypto_template *tmpl,

12
include/drm/i915_pciids.h
View File

@@ -237,13 +237,21 @@
#define INTEL_BDW_GT3D_IDS(info) \
_INTEL_BDW_D_IDS(3, info)
#define INTEL_BDW_RSVDM_IDS(info) \
_INTEL_BDW_M_IDS(4, info)
#define INTEL_BDW_RSVDD_IDS(info) \
_INTEL_BDW_D_IDS(4, info)
#define INTEL_BDW_M_IDS(info) \
INTEL_BDW_GT12M_IDS(info), \
INTEL_BDW_GT3M_IDS(info)
INTEL_BDW_GT3M_IDS(info), \
INTEL_BDW_RSVDM_IDS(info)
#define INTEL_BDW_D_IDS(info) \
INTEL_BDW_GT12D_IDS(info), \
INTEL_BDW_GT3D_IDS(info)
INTEL_BDW_GT3D_IDS(info), \
INTEL_BDW_RSVDD_IDS(info)
#define INTEL_CHV_IDS(info) \
INTEL_VGA_DEVICE(0x22b0, info), \

5
include/drm/i915_powerwell.h
View File

@@ -30,7 +30,8 @@
#define _I915_POWERWELL_H_
/* For use by hda_i915 driver */
extern void i915_request_power_well(void);
extern void i915_release_power_well(void);
extern int i915_request_power_well(void);
extern int i915_release_power_well(void);
extern int i915_get_cdclk_freq(void);
#endif /* _I915_POWERWELL_H_ */

40
include/dt-bindings/clk/ti-dra7-atl.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* This header provides constants for DRA7 ATL (Audio Tracking Logic)
*
* The constants defined in this header are used in dts files
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Peter Ujfalusi <peter.ujfalusi@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
#define _DT_BINDINGS_CLK_DRA7_ATL_H
#define DRA7_ATL_WS_MCASP1_FSR 0
#define DRA7_ATL_WS_MCASP1_FSX 1
#define DRA7_ATL_WS_MCASP2_FSR 2
#define DRA7_ATL_WS_MCASP2_FSX 3
#define DRA7_ATL_WS_MCASP3_FSX 4
#define DRA7_ATL_WS_MCASP4_FSX 5
#define DRA7_ATL_WS_MCASP5_FSX 6
#define DRA7_ATL_WS_MCASP6_FSX 7
#define DRA7_ATL_WS_MCASP7_FSX 8
#define DRA7_ATL_WS_MCASP8_FSX 9
#define DRA7_ATL_WS_MCASP8_AHCLKX 10
#define DRA7_ATL_WS_XREF_CLK3 11
#define DRA7_ATL_WS_XREF_CLK0 12
#define DRA7_ATL_WS_XREF_CLK1 13
#define DRA7_ATL_WS_XREF_CLK2 14
#define DRA7_ATL_WS_OSC1_X1 15
#endif

62
include/dt-bindings/clock/bcm21664.h Normal file
View File

@@ -0,0 +1,62 @@
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CLOCK_BCM21664_H
#define _CLOCK_BCM21664_H
/*
* This file defines the values used to specify clocks provided by
* the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
*/
/* bcm21664 CCU device tree "compatible" strings */
#define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu"
#define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu"
#define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu"
#define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu"
/* root CCU clock ids */
#define BCM21664_ROOT_CCU_FRAC_1M 0
#define BCM21664_ROOT_CCU_CLOCK_COUNT 1
/* aon CCU clock ids */
#define BCM21664_AON_CCU_HUB_TIMER 0
#define BCM21664_AON_CCU_CLOCK_COUNT 1
/* master CCU clock ids */
#define BCM21664_MASTER_CCU_SDIO1 0
#define BCM21664_MASTER_CCU_SDIO2 1
#define BCM21664_MASTER_CCU_SDIO3 2
#define BCM21664_MASTER_CCU_SDIO4 3
#define BCM21664_MASTER_CCU_SDIO1_SLEEP 4
#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5
#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6
#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7
#define BCM21664_MASTER_CCU_CLOCK_COUNT 8
/* slave CCU clock ids */
#define BCM21664_SLAVE_CCU_UARTB 0
#define BCM21664_SLAVE_CCU_UARTB2 1
#define BCM21664_SLAVE_CCU_UARTB3 2
#define BCM21664_SLAVE_CCU_BSC1 3
#define BCM21664_SLAVE_CCU_BSC2 4
#define BCM21664_SLAVE_CCU_BSC3 5
#define BCM21664_SLAVE_CCU_BSC4 6
#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7
#endif /* _CLOCK_BCM21664_H */

12
include/dt-bindings/clock/bcm281xx.h
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@@ -20,6 +20,18 @@
* the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
*/
/*
* These are the bcm281xx CCU device tree "compatible" strings.
* We're stuck with using "bcm11351" in the string because wild
* cards aren't allowed, and that name was the first one defined
* in this family of devices.
*/
#define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
#define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
#define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
#define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
#define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
/* root CCU clock ids */
#define BCM281XX_ROOT_CCU_FRAC_1M 0

45
include/dt-bindings/clock/berlin2.h Normal file
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@@ -0,0 +1,45 @@
/*
* Berlin2 BG2/BG2CD clock tree IDs
*/
#define CLKID_SYS 0
#define CLKID_CPU 1
#define CLKID_DRMFIGO 2
#define CLKID_CFG 3
#define CLKID_GFX 4
#define CLKID_ZSP 5
#define CLKID_PERIF 6
#define CLKID_PCUBE 7
#define CLKID_VSCOPE 8
#define CLKID_NFC_ECC 9
#define CLKID_VPP 10
#define CLKID_APP 11
#define CLKID_AUDIO0 12
#define CLKID_AUDIO2 13
#define CLKID_AUDIO3 14
#define CLKID_AUDIO1 15
#define CLKID_GFX3D_CORE 16
#define CLKID_GFX3D_SYS 17
#define CLKID_ARC 18
#define CLKID_VIP 19
#define CLKID_SDIO0XIN 20
#define CLKID_SDIO1XIN 21
#define CLKID_GFX3D_EXTRA 22
#define CLKID_GC360 23
#define CLKID_SDIO_DLLMST 24
#define CLKID_GETH0 25
#define CLKID_GETH1 26
#define CLKID_SATA 27
#define CLKID_AHBAPB 28
#define CLKID_USB0 29
#define CLKID_USB1 30
#define CLKID_PBRIDGE 31
#define CLKID_SDIO0 32
#define CLKID_SDIO1 33
#define CLKID_NFC 34
#define CLKID_SMEMC 35
#define CLKID_AUDIOHD 36
#define CLKID_VIDEO0 37
#define CLKID_VIDEO1 38
#define CLKID_VIDEO2 39
#define CLKID_TWD 40

31
include/dt-bindings/clock/berlin2q.h Normal file
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@@ -0,0 +1,31 @@
/*
* Berlin2 BG2Q clock tree IDs
*/
#define CLKID_SYS 0
#define CLKID_DRMFIGO 1
#define CLKID_CFG 2
#define CLKID_GFX2D 3
#define CLKID_ZSP 4
#define CLKID_PERIF 5
#define CLKID_PCUBE 6
#define CLKID_VSCOPE 7
#define CLKID_NFC_ECC 8
#define CLKID_VPP 9
#define CLKID_APP 10
#define CLKID_SDIO0XIN 11
#define CLKID_SDIO1XIN 12
#define CLKID_GFX2DAXI 13
#define CLKID_GETH0 14
#define CLKID_SATA 15
#define CLKID_AHBAPB 16
#define CLKID_USB0 17
#define CLKID_USB1 18
#define CLKID_USB2 19
#define CLKID_USB3 20
#define CLKID_PBRIDGE 21
#define CLKID_SDIO 22
#define CLKID_NFC 23
#define CLKID_SMEMC 24
#define CLKID_PCIE 25
#define CLKID_TWD 26

258
include/dt-bindings/clock/exynos3250.h Normal file
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@@ -0,0 +1,258 @@
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Tomasz Figa <t.figa@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung Exynos3250 clock controllers.
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
/*
* Let each exported clock get a unique index, which is used on DT-enabled
* platforms to lookup the clock from a clock specifier. These indices are
* therefore considered an ABI and so must not be changed. This implies
* that new clocks should be added either in free spaces between clock groups
* or at the end.
*/
/*
* Main CMU
*/
#define CLK_OSCSEL 1
#define CLK_FIN_PLL 2
#define CLK_FOUT_APLL 3
#define CLK_FOUT_VPLL 4
#define CLK_FOUT_UPLL 5
#define CLK_FOUT_MPLL 6
/* Muxes */
#define CLK_MOUT_MPLL_USER_L 16
#define CLK_MOUT_GDL 17
#define CLK_MOUT_MPLL_USER_R 18
#define CLK_MOUT_GDR 19
#define CLK_MOUT_EBI 20
#define CLK_MOUT_ACLK_200 21
#define CLK_MOUT_ACLK_160 22
#define CLK_MOUT_ACLK_100 23
#define CLK_MOUT_ACLK_266_1 24
#define CLK_MOUT_ACLK_266_0 25
#define CLK_MOUT_ACLK_266 26
#define CLK_MOUT_VPLL 27
#define CLK_MOUT_EPLL_USER 28
#define CLK_MOUT_EBI_1 29
#define CLK_MOUT_UPLL 30
#define CLK_MOUT_ACLK_400_MCUISP_SUB 31
#define CLK_MOUT_MPLL 32
#define CLK_MOUT_ACLK_400_MCUISP 33
#define CLK_MOUT_VPLLSRC 34
#define CLK_MOUT_CAM1 35
#define CLK_MOUT_CAM_BLK 36
#define CLK_MOUT_MFC 37
#define CLK_MOUT_MFC_1 38
#define CLK_MOUT_MFC_0 39
#define CLK_MOUT_G3D 40
#define CLK_MOUT_G3D_1 41
#define CLK_MOUT_G3D_0 42
#define CLK_MOUT_MIPI0 43
#define CLK_MOUT_FIMD0 44
#define CLK_MOUT_UART_ISP 45
#define CLK_MOUT_SPI1_ISP 46
#define CLK_MOUT_SPI0_ISP 47
#define CLK_MOUT_TSADC 48
#define CLK_MOUT_MMC1 49
#define CLK_MOUT_MMC0 50
#define CLK_MOUT_UART1 51
#define CLK_MOUT_UART0 52
#define CLK_MOUT_SPI1 53
#define CLK_MOUT_SPI0 54
#define CLK_MOUT_AUDIO 55
#define CLK_MOUT_MPLL_USER_C 56
#define CLK_MOUT_HPM 57
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
/* Dividers */
#define CLK_DIV_GPL 64
#define CLK_DIV_GDL 65
#define CLK_DIV_GPR 66
#define CLK_DIV_GDR 67
#define CLK_DIV_MPLL_PRE 68
#define CLK_DIV_ACLK_400_MCUISP 69
#define CLK_DIV_EBI 70
#define CLK_DIV_ACLK_200 71
#define CLK_DIV_ACLK_160 72
#define CLK_DIV_ACLK_100 73
#define CLK_DIV_ACLK_266 74
#define CLK_DIV_CAM1 75
#define CLK_DIV_CAM_BLK 76
#define CLK_DIV_MFC 77
#define CLK_DIV_G3D 78
#define CLK_DIV_MIPI0_PRE 79
#define CLK_DIV_MIPI0 80
#define CLK_DIV_FIMD0 81
#define CLK_DIV_UART_ISP 82
#define CLK_DIV_SPI1_ISP_PRE 83
#define CLK_DIV_SPI1_ISP 84
#define CLK_DIV_SPI0_ISP_PRE 85
#define CLK_DIV_SPI0_ISP 86
#define CLK_DIV_TSADC_PRE 87
#define CLK_DIV_TSADC 88
#define CLK_DIV_MMC1_PRE 89
#define CLK_DIV_MMC1 90
#define CLK_DIV_MMC0_PRE 91
#define CLK_DIV_MMC0 92
#define CLK_DIV_UART1 93
#define CLK_DIV_UART0 94
#define CLK_DIV_SPI1_PRE 95
#define CLK_DIV_SPI1 96
#define CLK_DIV_SPI0_PRE 97
#define CLK_DIV_SPI0 98
#define CLK_DIV_PCM 99
#define CLK_DIV_AUDIO 100
#define CLK_DIV_I2S 101
#define CLK_DIV_CORE2 102
#define CLK_DIV_APLL 103
#define CLK_DIV_PCLK_DBG 104
#define CLK_DIV_ATB 105
#define CLK_DIV_COREM 106
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
/* Gates */
#define CLK_ASYNC_G3D 128
#define CLK_ASYNC_MFCL 129
#define CLK_PPMULEFT 130
#define CLK_GPIO_LEFT 131
#define CLK_ASYNC_ISPMX 132
#define CLK_ASYNC_FSYSD 133
#define CLK_ASYNC_LCD0X 134
#define CLK_ASYNC_CAMX 135
#define CLK_PPMURIGHT 136
#define CLK_GPIO_RIGHT 137
#define CLK_MONOCNT 138
#define CLK_TZPC6 139
#define CLK_PROVISIONKEY1 140
#define CLK_PROVISIONKEY0 141
#define CLK_CMU_ISPPART 142
#define CLK_TMU_APBIF 143
#define CLK_KEYIF 144
#define CLK_RTC 145
#define CLK_WDT 146
#define CLK_MCT 147
#define CLK_SECKEY 148
#define CLK_TZPC5 149
#define CLK_TZPC4 150
#define CLK_TZPC3 151
#define CLK_TZPC2 152
#define CLK_TZPC1 153
#define CLK_TZPC0 154
#define CLK_CMU_COREPART 155
#define CLK_CMU_TOPPART 156
#define CLK_PMU_APBIF 157
#define CLK_SYSREG 158
#define CLK_CHIP_ID 159
#define CLK_QEJPEG 160
#define CLK_PIXELASYNCM1 161
#define CLK_PIXELASYNCM0 162
#define CLK_PPMUCAMIF 163
#define CLK_QEM2MSCALER 164
#define CLK_QEGSCALER1 165
#define CLK_QEGSCALER0 166
#define CLK_SMMUJPEG 167
#define CLK_SMMUM2M2SCALER 168
#define CLK_SMMUGSCALER1 169
#define CLK_SMMUGSCALER0 170
#define CLK_JPEG 171
#define CLK_M2MSCALER 172
#define CLK_GSCALER1 173
#define CLK_GSCALER0 174
#define CLK_QEMFC 175
#define CLK_PPMUMFC_L 176
#define CLK_SMMUMFC_L 177
#define CLK_MFC 178
#define CLK_SMMUG3D 179
#define CLK_QEG3D 180
#define CLK_PPMUG3D 181
#define CLK_G3D 182
#define CLK_QE_CH1_LCD 183
#define CLK_QE_CH0_LCD 184
#define CLK_PPMULCD0 185
#define CLK_SMMUFIMD0 186
#define CLK_DSIM0 187
#define CLK_FIMD0 188
#define CLK_CAM1 189
#define CLK_UART_ISP_TOP 190
#define CLK_SPI1_ISP_TOP 191
#define CLK_SPI0_ISP_TOP 192
#define CLK_TSADC 193
#define CLK_PPMUFILE 194
#define CLK_USBOTG 195
#define CLK_USBHOST 196
#define CLK_SROMC 197
#define CLK_SDMMC1 198
#define CLK_SDMMC0 199
#define CLK_PDMA1 200
#define CLK_PDMA0 201
#define CLK_PWM 202
#define CLK_PCM 203
#define CLK_I2S 204
#define CLK_SPI1 205
#define CLK_SPI0 206
#define CLK_I2C7 207
#define CLK_I2C6 208
#define CLK_I2C5 209
#define CLK_I2C4 210
#define CLK_I2C3 211
#define CLK_I2C2 212
#define CLK_I2C1 213
#define CLK_I2C0 214
#define CLK_UART1 215
#define CLK_UART0 216
#define CLK_BLOCK_LCD 217
#define CLK_BLOCK_G3D 218
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
/* Special clocks */
#define CLK_SCLK_JPEG 224
#define CLK_SCLK_M2MSCALER 225
#define CLK_SCLK_GSCALER1 226
#define CLK_SCLK_GSCALER0 227
#define CLK_SCLK_MFC 228
#define CLK_SCLK_G3D 229
#define CLK_SCLK_MIPIDPHY2L 230
#define CLK_SCLK_MIPI0 231
#define CLK_SCLK_FIMD0 232
#define CLK_SCLK_CAM1 233
#define CLK_SCLK_UART_ISP 234
#define CLK_SCLK_SPI1_ISP 235
#define CLK_SCLK_SPI0_ISP 236
#define CLK_SCLK_UPLL 237
#define CLK_SCLK_TSADC 238
#define CLK_SCLK_EBI 239
#define CLK_SCLK_MMC1 240
#define CLK_SCLK_MMC0 241
#define CLK_SCLK_I2S 242
#define CLK_SCLK_PCM 243
#define CLK_SCLK_SPI1 244
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define CLK_NR_CLKS 248
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

2
include/dt-bindings/clock/exynos4.h
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@@ -33,6 +33,7 @@
#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
#define CLK_MOUT_CORE 19
#define CLK_MOUT_APLL 20
#define CLK_SCLK_HDMIPHY 22
/* gate for special clocks (sclk) */
#define CLK_SCLK_FIMC0 128
@@ -181,7 +182,6 @@
#define CLK_KEYIF 347
#define CLK_AUDSS 348
#define CLK_MIPI_HSI 349 /* Exynos4210 only */
#define CLK_MDMA2 350 /* Exynos4210 only */
#define CLK_PIXELASYNCM0 351
#define CLK_PIXELASYNCM1 352
#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */

21
include/dt-bindings/clock/exynos5250.h
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@@ -150,11 +150,30 @@
#define CLK_G2D 345
#define CLK_MDMA0 346
#define CLK_SMMU_MDMA0 347
#define CLK_SSS 348
#define CLK_G3D 349
#define CLK_SMMU_TV 350
#define CLK_SMMU_FIMD1 351
#define CLK_SMMU_2D 352
#define CLK_SMMU_FIMC_ISP 353
#define CLK_SMMU_FIMC_DRC 354
#define CLK_SMMU_FIMC_SCC 355
#define CLK_SMMU_FIMC_SCP 356
#define CLK_SMMU_FIMC_FD 357
#define CLK_SMMU_FIMC_MCU 358
#define CLK_SMMU_FIMC_ODC 359
#define CLK_SMMU_FIMC_DIS0 360
#define CLK_SMMU_FIMC_DIS1 361
#define CLK_SMMU_FIMC_3DNR 362
#define CLK_SMMU_FIMC_LITE0 363
#define CLK_SMMU_FIMC_LITE1 364
#define CLK_CAMIF_TOP 365
/* mux clocks */
#define CLK_MOUT_HDMI 1024
#define CLK_MOUT_GPLL 1025
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 1025
#define CLK_NR_CLKS 1026
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

469
include/dt-bindings/clock/exynos5260-clk.h Normal file
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@@ -0,0 +1,469 @@
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Rahul Sharma <rahul.sharma@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Provides Constants for Exynos5260 clocks.
*/
#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
#define _DT_BINDINGS_CLK_EXYNOS5260_H
/* Clock names: <cmu><type><IP> */
/* List Of Clocks For CMU_TOP */
#define TOP_FOUT_DISP_PLL 1
#define TOP_FOUT_AUD_PLL 2
#define TOP_MOUT_AUDTOP_PLL_USER 3
#define TOP_MOUT_AUD_PLL 4
#define TOP_MOUT_DISP_PLL 5
#define TOP_MOUT_BUSTOP_PLL_USER 6
#define TOP_MOUT_MEMTOP_PLL_USER 7
#define TOP_MOUT_MEDIATOP_PLL_USER 8
#define TOP_MOUT_DISP_DISP_333 9
#define TOP_MOUT_ACLK_DISP_333 10
#define TOP_MOUT_DISP_DISP_222 11
#define TOP_MOUT_ACLK_DISP_222 12
#define TOP_MOUT_DISP_MEDIA_PIXEL 13
#define TOP_MOUT_FIMD1 14
#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15
#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16
#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17
#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18
#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19
#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20
#define TOP_MOUT_BUS4_BUSTOP_100 21
#define TOP_MOUT_BUS4_BUSTOP_400 22
#define TOP_MOUT_BUS3_BUSTOP_100 23
#define TOP_MOUT_BUS3_BUSTOP_400 24
#define TOP_MOUT_BUS2_BUSTOP_400 25
#define TOP_MOUT_BUS2_BUSTOP_100 26
#define TOP_MOUT_BUS1_BUSTOP_100 27
#define TOP_MOUT_BUS1_BUSTOP_400 28
#define TOP_MOUT_SCLK_FSYS_USB 29
#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30
#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31
#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32
#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33
#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34
#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35
#define TOP_MOUT_ACLK_ISP1_266 36
#define TOP_MOUT_ISP1_MEDIA_266 37
#define TOP_MOUT_ACLK_ISP1_400 38
#define TOP_MOUT_ISP1_MEDIA_400 39
#define TOP_MOUT_SCLK_ISP1_SPI0 40
#define TOP_MOUT_SCLK_ISP1_SPI1 41
#define TOP_MOUT_SCLK_ISP1_UART 42
#define TOP_MOUT_SCLK_ISP1_SENSOR2 43
#define TOP_MOUT_SCLK_ISP1_SENSOR1 44
#define TOP_MOUT_SCLK_ISP1_SENSOR0 45
#define TOP_MOUT_ACLK_MFC_333 46
#define TOP_MOUT_MFC_BUSTOP_333 47
#define TOP_MOUT_ACLK_G2D_333 48
#define TOP_MOUT_G2D_BUSTOP_333 49
#define TOP_MOUT_ACLK_GSCL_FIMC 50
#define TOP_MOUT_GSCL_BUSTOP_FIMC 51
#define TOP_MOUT_ACLK_GSCL_333 52
#define TOP_MOUT_GSCL_BUSTOP_333 53
#define TOP_MOUT_ACLK_GSCL_400 54
#define TOP_MOUT_M2M_MEDIATOP_400 55
#define TOP_DOUT_ACLK_MFC_333 56
#define TOP_DOUT_ACLK_G2D_333 57
#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58
#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59
#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60
#define TOP_DOUT_ACLK_GSCL_FIMC 61
#define TOP_DOUT_ACLK_GSCL_400 62
#define TOP_DOUT_ACLK_GSCL_333 63
#define TOP_DOUT_SCLK_ISP1_SPI0_B 64
#define TOP_DOUT_SCLK_ISP1_SPI0_A 65
#define TOP_DOUT_ACLK_ISP1_400 66
#define TOP_DOUT_ACLK_ISP1_266 67
#define TOP_DOUT_SCLK_ISP1_UART 68
#define TOP_DOUT_SCLK_ISP1_SPI1_B 69
#define TOP_DOUT_SCLK_ISP1_SPI1_A 70
#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71
#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72
#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73
#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74
#define TOP_DOUT_SCLK_DISP_PIXEL 75
#define TOP_DOUT_ACLK_DISP_222 76
#define TOP_DOUT_ACLK_DISP_333 77
#define TOP_DOUT_ACLK_BUS4_100 78
#define TOP_DOUT_ACLK_BUS4_400 79
#define TOP_DOUT_ACLK_BUS3_100 80
#define TOP_DOUT_ACLK_BUS3_400 81
#define TOP_DOUT_ACLK_BUS2_100 82
#define TOP_DOUT_ACLK_BUS2_400 83
#define TOP_DOUT_ACLK_BUS1_100 84
#define TOP_DOUT_ACLK_BUS1_400 85
#define TOP_DOUT_SCLK_PERI_SPI1_B 86
#define TOP_DOUT_SCLK_PERI_SPI1_A 87
#define TOP_DOUT_SCLK_PERI_SPI0_B 88
#define TOP_DOUT_SCLK_PERI_SPI0_A 89
#define TOP_DOUT_SCLK_PERI_UART0 90
#define TOP_DOUT_SCLK_PERI_UART2 91
#define TOP_DOUT_SCLK_PERI_UART1 92
#define TOP_DOUT_SCLK_PERI_SPI2_B 93
#define TOP_DOUT_SCLK_PERI_SPI2_A 94
#define TOP_DOUT_ACLK_PERI_AUD 95
#define TOP_DOUT_ACLK_PERI_66 96
#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97
#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98
#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99
#define TOP_DOUT_ACLK_FSYS_200 100
#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101
#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102
#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103
#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104
#define TOP_SCLK_FIMD1 105
#define TOP_SCLK_MMC2 106
#define TOP_SCLK_MMC1 107
#define TOP_SCLK_MMC0 108
#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109
#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110
#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111
#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112
#define phyclk_hdmi_phy_tmds_clko 113
#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114
#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115
#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116
#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117
#define PHYCLK_DPTX_PHY_CLK_DIV2 118
#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119
#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120
#define PHYCLK_USBHOST20_PHY_FREECLK 121
#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122
#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123
#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124
#define TOP_NR_CLK 125
/* List Of Clocks For CMU_EGL */
#define EGL_FOUT_EGL_PLL 1
#define EGL_FOUT_EGL_DPLL 2
#define EGL_MOUT_EGL_B 3
#define EGL_MOUT_EGL_PLL 4
#define EGL_DOUT_EGL_PLL 5
#define EGL_DOUT_EGL_PCLK_DBG 6
#define EGL_DOUT_EGL_ATCLK 7
#define EGL_DOUT_PCLK_EGL 8
#define EGL_DOUT_ACLK_EGL 9
#define EGL_DOUT_EGL2 10
#define EGL_DOUT_EGL1 11
#define EGL_NR_CLK 12
/* List Of Clocks For CMU_KFC */
#define KFC_FOUT_KFC_PLL 1
#define KFC_MOUT_KFC_PLL 2
#define KFC_MOUT_KFC 3
#define KFC_DOUT_KFC_PLL 4
#define KFC_DOUT_PCLK_KFC 5
#define KFC_DOUT_ACLK_KFC 6
#define KFC_DOUT_KFC_PCLK_DBG 7
#define KFC_DOUT_KFC_ATCLK 8
#define KFC_DOUT_KFC2 9
#define KFC_DOUT_KFC1 10
#define KFC_NR_CLK 11
/* List Of Clocks For CMU_MIF */
#define MIF_FOUT_MEM_PLL 1
#define MIF_FOUT_MEDIA_PLL 2
#define MIF_FOUT_BUS_PLL 3
#define MIF_MOUT_CLK2X_PHY 4
#define MIF_MOUT_MIF_DREX2X 5
#define MIF_MOUT_CLKM_PHY 6
#define MIF_MOUT_MIF_DREX 7
#define MIF_MOUT_MEDIA_PLL 8
#define MIF_MOUT_BUS_PLL 9
#define MIF_MOUT_MEM_PLL 10
#define MIF_DOUT_ACLK_BUS_100 11
#define MIF_DOUT_ACLK_BUS_200 12
#define MIF_DOUT_ACLK_MIF_466 13
#define MIF_DOUT_CLK2X_PHY 14
#define MIF_DOUT_CLKM_PHY 15
#define MIF_DOUT_BUS_PLL 16
#define MIF_DOUT_MEM_PLL 17
#define MIF_DOUT_MEDIA_PLL 18
#define MIF_CLK_LPDDR3PHY_WRAP1 19
#define MIF_CLK_LPDDR3PHY_WRAP0 20
#define MIF_CLK_MONOCNT 21
#define MIF_CLK_MIF_RTC 22
#define MIF_CLK_DREX1 23
#define MIF_CLK_DREX0 24
#define MIF_CLK_INTMEM 25
#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26
#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27
#define MIF_NR_CLK 28
/* List Of Clocks For CMU_G3D */
#define G3D_FOUT_G3D_PLL 1
#define G3D_MOUT_G3D_PLL 2
#define G3D_DOUT_PCLK_G3D 3
#define G3D_DOUT_ACLK_G3D 4
#define G3D_CLK_G3D_HPM 5
#define G3D_CLK_G3D 6
#define G3D_NR_CLK 7
/* List Of Clocks For CMU_AUD */
#define AUD_MOUT_SCLK_AUD_PCM 1
#define AUD_MOUT_SCLK_AUD_I2S 2
#define AUD_MOUT_AUD_PLL_USER 3
#define AUD_DOUT_ACLK_AUD_131 4
#define AUD_DOUT_SCLK_AUD_UART 5
#define AUD_DOUT_SCLK_AUD_PCM 6
#define AUD_DOUT_SCLK_AUD_I2S 7
#define AUD_CLK_AUD_UART 8
#define AUD_CLK_PCM 9
#define AUD_CLK_I2S 10
#define AUD_CLK_DMAC 11
#define AUD_CLK_SRAMC 12
#define AUD_SCLK_AUD_UART 13
#define AUD_SCLK_PCM 14
#define AUD_SCLK_I2S 15
#define AUD_NR_CLK 16
/* List Of Clocks For CMU_MFC */
#define MFC_MOUT_ACLK_MFC_333_USER 1
#define MFC_DOUT_PCLK_MFC_83 2
#define MFC_CLK_MFC 3
#define MFC_CLK_SMMU2_MFCM1 4
#define MFC_CLK_SMMU2_MFCM0 5
#define MFC_NR_CLK 6
/* List Of Clocks For CMU_GSCL */
#define GSCL_MOUT_ACLK_CSIS 1
#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2
#define GSCL_MOUT_ACLK_M2M_400_USER 3
#define GSCL_MOUT_ACLK_GSCL_333_USER 4
#define GSCL_DOUT_ACLK_CSIS_200 5
#define GSCL_DOUT_PCLK_M2M_100 6
#define GSCL_CLK_PIXEL_GSCL1 7
#define GSCL_CLK_PIXEL_GSCL0 8
#define GSCL_CLK_MSCL1 9
#define GSCL_CLK_MSCL0 10
#define GSCL_CLK_GSCL1 11
#define GSCL_CLK_GSCL0 12
#define GSCL_CLK_FIMC_LITE_D 13
#define GSCL_CLK_FIMC_LITE_B 14
#define GSCL_CLK_FIMC_LITE_A 15
#define GSCL_CLK_CSIS1 16
#define GSCL_CLK_CSIS0 17
#define GSCL_CLK_SMMU3_LITE_D 18
#define GSCL_CLK_SMMU3_LITE_B 19
#define GSCL_CLK_SMMU3_LITE_A 20
#define GSCL_CLK_SMMU3_GSCL0 21
#define GSCL_CLK_SMMU3_GSCL1 22
#define GSCL_CLK_SMMU3_MSCL0 23
#define GSCL_CLK_SMMU3_MSCL1 24
#define GSCL_SCLK_CSIS1_WRAP 25
#define GSCL_SCLK_CSIS0_WRAP 26
#define GSCL_NR_CLK 27
/* List Of Clocks For CMU_FSYS */
#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1
#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2
#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3
#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4
#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5
#define FSYS_CLK_TSI 6
#define FSYS_CLK_USBLINK 7
#define FSYS_CLK_USBHOST20 8
#define FSYS_CLK_USBDRD30 9
#define FSYS_CLK_SROMC 10
#define FSYS_CLK_PDMA 11
#define FSYS_CLK_MMC2 12
#define FSYS_CLK_MMC1 13
#define FSYS_CLK_MMC0 14
#define FSYS_CLK_RTIC 15
#define FSYS_CLK_SMMU_RTIC 16
#define FSYS_PHYCLK_USBDRD30 17
#define FSYS_PHYCLK_USBHOST20 18
#define FSYS_NR_CLK 19
/* List Of Clocks For CMU_PERI */
#define PERI_MOUT_SCLK_SPDIF 1
#define PERI_MOUT_SCLK_I2SCOD 2
#define PERI_MOUT_SCLK_PCM 3
#define PERI_DOUT_I2S 4
#define PERI_DOUT_PCM 5
#define PERI_CLK_WDT_KFC 6
#define PERI_CLK_WDT_EGL 7
#define PERI_CLK_HSIC3 8
#define PERI_CLK_HSIC2 9
#define PERI_CLK_HSIC1 10
#define PERI_CLK_HSIC0 11
#define PERI_CLK_PCM 12
#define PERI_CLK_MCT 13
#define PERI_CLK_I2S 14
#define PERI_CLK_I2CHDMI 15
#define PERI_CLK_I2C7 16
#define PERI_CLK_I2C6 17
#define PERI_CLK_I2C5 18
#define PERI_CLK_I2C4 19
#define PERI_CLK_I2C9 20
#define PERI_CLK_I2C8 21
#define PERI_CLK_I2C11 22
#define PERI_CLK_I2C10 23
#define PERI_CLK_HDMICEC 24
#define PERI_CLK_EFUSE_WRITER 25
#define PERI_CLK_ABB 26
#define PERI_CLK_UART2 27
#define PERI_CLK_UART1 28
#define PERI_CLK_UART0 29
#define PERI_CLK_ADC 30
#define PERI_CLK_TMU4 31
#define PERI_CLK_TMU3 32
#define PERI_CLK_TMU2 33
#define PERI_CLK_TMU1 34
#define PERI_CLK_TMU0 35
#define PERI_CLK_SPI2 36
#define PERI_CLK_SPI1 37
#define PERI_CLK_SPI0 38
#define PERI_CLK_SPDIF 39
#define PERI_CLK_PWM 40
#define PERI_CLK_UART4 41
#define PERI_CLK_CHIPID 42
#define PERI_CLK_PROVKEY0 43
#define PERI_CLK_PROVKEY1 44
#define PERI_CLK_SECKEY 45
#define PERI_CLK_TOP_RTC 46
#define PERI_CLK_TZPC10 47
#define PERI_CLK_TZPC9 48
#define PERI_CLK_TZPC8 49
#define PERI_CLK_TZPC7 50
#define PERI_CLK_TZPC6 51
#define PERI_CLK_TZPC5 52
#define PERI_CLK_TZPC4 53
#define PERI_CLK_TZPC3 54
#define PERI_CLK_TZPC2 55
#define PERI_CLK_TZPC1 56
#define PERI_CLK_TZPC0 57
#define PERI_SCLK_UART2 58
#define PERI_SCLK_UART1 59
#define PERI_SCLK_UART0 60
#define PERI_SCLK_SPI2 61
#define PERI_SCLK_SPI1 62
#define PERI_SCLK_SPI0 63
#define PERI_SCLK_SPDIF 64
#define PERI_SCLK_I2S 65
#define PERI_SCLK_PCM1 66
#define PERI_NR_CLK 67
/* List Of Clocks For CMU_DISP */
#define DISP_MOUT_SCLK_HDMI_SPDIF 1
#define DISP_MOUT_SCLK_HDMI_PIXEL 2
#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3
#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4
#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5
#define DISP_MOUT_HDMI_PHY_PIXEL 6
#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7
#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8
#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9
#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10
#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11
#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12
#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13
#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14
#define DISP_MOUT_ACLK_DISP_222_USER 15
#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16
#define DISP_MOUT_ACLK_DISP_333_USER 17
#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18
#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19
#define DISP_DOUT_PCLK_DISP_111 20
#define DISP_CLK_SMMU_TV 21
#define DISP_CLK_SMMU_FIMD1M1 22
#define DISP_CLK_SMMU_FIMD1M0 23
#define DISP_CLK_PIXEL_MIXER 24
#define DISP_CLK_PIXEL_DISP 25
#define DISP_CLK_MIXER 26
#define DISP_CLK_MIPIPHY 27
#define DISP_CLK_HDMIPHY 28
#define DISP_CLK_HDMI 29
#define DISP_CLK_FIMD1 30
#define DISP_CLK_DSIM1 31
#define DISP_CLK_DPPHY 32
#define DISP_CLK_DP 33
#define DISP_SCLK_PIXEL 34
#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35
#define DISP_NR_CLK 36
/* List Of Clocks For CMU_G2D */
#define G2D_MOUT_ACLK_G2D_333_USER 1
#define G2D_DOUT_PCLK_G2D_83 2
#define G2D_CLK_SMMU3_JPEG 3
#define G2D_CLK_MDMA 4
#define G2D_CLK_JPEG 5
#define G2D_CLK_G2D 6
#define G2D_CLK_SSS 7
#define G2D_CLK_SLIM_SSS 8
#define G2D_CLK_SMMU_SLIM_SSS 9
#define G2D_CLK_SMMU_SSS 10
#define G2D_CLK_SMMU_MDMA 11
#define G2D_CLK_SMMU3_G2D 12
#define G2D_NR_CLK 13
/* List Of Clocks For CMU_ISP */
#define ISP_MOUT_ISP_400_USER 1
#define ISP_MOUT_ISP_266_USER 2
#define ISP_DOUT_SCLK_MPWM 3
#define ISP_DOUT_CA5_PCLKDBG 4
#define ISP_DOUT_CA5_ATCLKIN 5
#define ISP_DOUT_PCLK_ISP_133 6
#define ISP_DOUT_PCLK_ISP_66 7
#define ISP_CLK_GIC 8
#define ISP_CLK_WDT 9
#define ISP_CLK_UART 10
#define ISP_CLK_SPI1 11
#define ISP_CLK_SPI0 12
#define ISP_CLK_SMMU_SCALERP 13
#define ISP_CLK_SMMU_SCALERC 14
#define ISP_CLK_SMMU_ISPCX 15
#define ISP_CLK_SMMU_ISP 16
#define ISP_CLK_SMMU_FD 17
#define ISP_CLK_SMMU_DRC 18
#define ISP_CLK_PWM 19
#define ISP_CLK_MTCADC 20
#define ISP_CLK_MPWM 21
#define ISP_CLK_MCUCTL 22
#define ISP_CLK_I2C1 23
#define ISP_CLK_I2C0 24
#define ISP_CLK_FIMC_SCALERP 25
#define ISP_CLK_FIMC_SCALERC 26
#define ISP_CLK_FIMC 27
#define ISP_CLK_FIMC_FD 28
#define ISP_CLK_FIMC_DRC 29
#define ISP_CLK_CA5 30
#define ISP_SCLK_SPI0_EXT 31
#define ISP_SCLK_SPI1_EXT 32
#define ISP_SCLK_UART_EXT 33
#define ISP_NR_CLK 34
#endif

33
include/dt-bindings/clock/exynos5410.h Normal file
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@@ -0,0 +1,33 @@
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
/* core clocks */
#define CLK_FIN_PLL 1
#define CLK_FOUT_APLL 2
#define CLK_FOUT_CPLL 3
#define CLK_FOUT_MPLL 4
#define CLK_FOUT_BPLL 5
#define CLK_FOUT_KPLL 6
/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
#define CLK_SCLK_UART1 129
#define CLK_SCLK_UART2 130
#define CLK_SCLK_UART3 131
#define CLK_SCLK_MMC0 132
#define CLK_SCLK_MMC1 133
#define CLK_SCLK_MMC2 134
/* gate clocks */
#define CLK_UART0 257
#define CLK_UART1 258
#define CLK_UART2 259
#define CLK_UART3 260
#define CLK_MCT 315
#define CLK_MMC0 351
#define CLK_MMC1 352
#define CLK_MMC2 353
#define CLK_NR_CLKS 512
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */

43
include/dt-bindings/clock/exynos5420.h
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@@ -58,6 +58,9 @@
#define CLK_SCLK_GSCL_WA 156
#define CLK_SCLK_GSCL_WB 157
#define CLK_SCLK_HDMIPHY 158
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
/* gate clocks */
#define CLK_ACLK66_PERIC 256
@@ -69,10 +72,10 @@
#define CLK_I2C1 262
#define CLK_I2C2 263
#define CLK_I2C3 264
#define CLK_I2C4 265
#define CLK_I2C5 266
#define CLK_I2C6 267
#define CLK_I2C7 268
#define CLK_USI0 265
#define CLK_USI1 266
#define CLK_USI2 267
#define CLK_USI3 268
#define CLK_I2C_HDMI 269
#define CLK_TSADC 270
#define CLK_SPI0 271
@@ -85,9 +88,9 @@
#define CLK_PCM2 278
#define CLK_PWM 279
#define CLK_SPDIF 280
#define CLK_I2C8 281
#define CLK_I2C9 282
#define CLK_I2C10 283
#define CLK_USI4 281
#define CLK_USI5 282
#define CLK_USI6 283
#define CLK_ACLK66_PSGEN 300
#define CLK_CHIPID 301
#define CLK_SYSREG 302
@@ -140,7 +143,8 @@
#define CLK_HDMI 413
#define CLK_ACLK300_DISP1 420
#define CLK_FIMD1 421
#define CLK_SMMU_FIMD1 422
#define CLK_SMMU_FIMD1M0 422
#define CLK_SMMU_FIMD1M1 423
#define CLK_ACLK166 430
#define CLK_MIXER 431
#define CLK_ACLK266 440
@@ -152,6 +156,7 @@
#define CLK_JPEG 451
#define CLK_JPEG2 452
#define CLK_SMMU_JPEG 453
#define CLK_SMMU_JPEG2 454
#define CLK_ACLK300_GSCL 460
#define CLK_SMMU_GSCL0 461
#define CLK_SMMU_GSCL1 462
@@ -159,7 +164,7 @@
#define CLK_GSCL_WB 464
#define CLK_GSCL0 465
#define CLK_GSCL1 466
#define CLK_CLK_3AA 467
#define CLK_FIMC_3AA 467
#define CLK_ACLK266_G2D 470
#define CLK_SSS 471
#define CLK_SLIM_SSS 472
@@ -172,12 +177,32 @@
#define CLK_SMMU_FIMCL1 493
#define CLK_SMMU_FIMCL3 494
#define CLK_FIMC_LITE3 495
#define CLK_FIMC_LITE0 496
#define CLK_FIMC_LITE1 497
#define CLK_ACLK_G3D 500
#define CLK_G3D 501
#define CLK_SMMU_MIXER 502
#define CLK_SMMU_G2D 503
#define CLK_SMMU_MDMA0 504
#define CLK_MC 505
#define CLK_TOP_RTC 506
#define CLK_SCLK_UART_ISP 510
#define CLK_SCLK_SPI0_ISP 511
#define CLK_SCLK_SPI1_ISP 512
#define CLK_SCLK_PWM_ISP 513
#define CLK_SCLK_ISP_SENSOR0 514
#define CLK_SCLK_ISP_SENSOR1 515
#define CLK_SCLK_ISP_SENSOR2 516
#define CLK_ACLK432_SCALER 517
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
/* mux clocks */
#define CLK_MOUT_HDMI 640
#define CLK_MOUT_G3D 641
#define CLK_MOUT_VPLL 642
#define CLK_MOUT_MAUDIO0 643
/* divider clocks */
#define CLK_DOUT_PIXEL 768

58
include/dt-bindings/clock/hix5hd2-clock.h Normal file
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@@ -0,0 +1,58 @@
/*
* Copyright (c) 2014 Linaro Ltd.
* Copyright (c) 2014 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#ifndef __DTS_HIX5HD2_CLOCK_H
#define __DTS_HIX5HD2_CLOCK_H
/* fixed rate */
#define HIX5HD2_FIXED_1200M 1
#define HIX5HD2_FIXED_400M 2
#define HIX5HD2_FIXED_48M 3
#define HIX5HD2_FIXED_24M 4
#define HIX5HD2_FIXED_600M 5
#define HIX5HD2_FIXED_300M 6
#define HIX5HD2_FIXED_75M 7
#define HIX5HD2_FIXED_200M 8
#define HIX5HD2_FIXED_100M 9
#define HIX5HD2_FIXED_40M 10
#define HIX5HD2_FIXED_150M 11
#define HIX5HD2_FIXED_1728M 12
#define HIX5HD2_FIXED_28P8M 13
#define HIX5HD2_FIXED_432M 14
#define HIX5HD2_FIXED_345P6M 15
#define HIX5HD2_FIXED_288M 16
#define HIX5HD2_FIXED_60M 17
#define HIX5HD2_FIXED_750M 18
#define HIX5HD2_FIXED_500M 19
#define HIX5HD2_FIXED_54M 20
#define HIX5HD2_FIXED_27M 21
#define HIX5HD2_FIXED_1500M 22
#define HIX5HD2_FIXED_375M 23
#define HIX5HD2_FIXED_187M 24
#define HIX5HD2_FIXED_250M 25
#define HIX5HD2_FIXED_125M 26
#define HIX5HD2_FIXED_2P02M 27
#define HIX5HD2_FIXED_50M 28
#define HIX5HD2_FIXED_25M 29
#define HIX5HD2_FIXED_83M 30
/* mux clocks */
#define HIX5HD2_SFC_MUX 64
#define HIX5HD2_MMC_MUX 65
#define HIX5HD2_FEPHY_MUX 66
/* gate clocks */
#define HIX5HD2_SFC_RST 128
#define HIX5HD2_SFC_CLK 129
#define HIX5HD2_MMC_CIU_CLK 130
#define HIX5HD2_MMC_BIU_CLK 131
#define HIX5HD2_MMC_CIU_RST 132
#define HIX5HD2_NR_CLKS 256
#endif /* __DTS_HIX5HD2_CLOCK_H */

3
include/dt-bindings/clock/imx6sl-clock.h
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@@ -145,6 +145,7 @@
#define IMX6SL_CLK_USDHC4 132
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
#define IMX6SL_CLK_SPBA 134
#define IMX6SL_CLK_END 135
#define IMX6SL_CLK_ENET 135
#define IMX6SL_CLK_END 136
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

256
include/dt-bindings/clock/imx6sx-clock.h Normal file
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@@ -0,0 +1,256 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
#define __DT_BINDINGS_CLOCK_IMX6SX_H
#define IMX6SX_CLK_DUMMY 0
#define IMX6SX_CLK_CKIL 1
#define IMX6SX_CLK_CKIH 2
#define IMX6SX_CLK_OSC 3
#define IMX6SX_CLK_PLL1_SYS 4
#define IMX6SX_CLK_PLL2_BUS 5
#define IMX6SX_CLK_PLL3_USB_OTG 6
#define IMX6SX_CLK_PLL4_AUDIO 7
#define IMX6SX_CLK_PLL5_VIDEO 8
#define IMX6SX_CLK_PLL6_ENET 9
#define IMX6SX_CLK_PLL7_USB_HOST 10
#define IMX6SX_CLK_USBPHY1 11
#define IMX6SX_CLK_USBPHY2 12
#define IMX6SX_CLK_USBPHY1_GATE 13
#define IMX6SX_CLK_USBPHY2_GATE 14
#define IMX6SX_CLK_PCIE_REF 15
#define IMX6SX_CLK_PCIE_REF_125M 16
#define IMX6SX_CLK_ENET_REF 17
#define IMX6SX_CLK_PLL2_PFD0 18
#define IMX6SX_CLK_PLL2_PFD1 19
#define IMX6SX_CLK_PLL2_PFD2 20
#define IMX6SX_CLK_PLL2_PFD3 21
#define IMX6SX_CLK_PLL3_PFD0 22
#define IMX6SX_CLK_PLL3_PFD1 23
#define IMX6SX_CLK_PLL3_PFD2 24
#define IMX6SX_CLK_PLL3_PFD3 25
#define IMX6SX_CLK_PLL2_198M 26
#define IMX6SX_CLK_PLL3_120M 27
#define IMX6SX_CLK_PLL3_80M 28
#define IMX6SX_CLK_PLL3_60M 29
#define IMX6SX_CLK_TWD 30
#define IMX6SX_CLK_PLL4_POST_DIV 31
#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
#define IMX6SX_CLK_PLL5_POST_DIV 33
#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
#define IMX6SX_CLK_STEP 35
#define IMX6SX_CLK_PLL1_SW 36
#define IMX6SX_CLK_OCRAM_SEL 37
#define IMX6SX_CLK_PERIPH_PRE 38
#define IMX6SX_CLK_PERIPH2_PRE 39
#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
#define IMX6SX_CLK_PCIE_AXI_SEL 42
#define IMX6SX_CLK_GPU_AXI_SEL 43
#define IMX6SX_CLK_GPU_CORE_SEL 44
#define IMX6SX_CLK_EIM_SLOW_SEL 45
#define IMX6SX_CLK_USDHC1_SEL 46
#define IMX6SX_CLK_USDHC2_SEL 47
#define IMX6SX_CLK_USDHC3_SEL 48
#define IMX6SX_CLK_USDHC4_SEL 49
#define IMX6SX_CLK_SSI1_SEL 50
#define IMX6SX_CLK_SSI2_SEL 51
#define IMX6SX_CLK_SSI3_SEL 52
#define IMX6SX_CLK_QSPI1_SEL 53
#define IMX6SX_CLK_PERCLK_SEL 54
#define IMX6SX_CLK_VID_SEL 55
#define IMX6SX_CLK_ESAI_SEL 56
#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
#define IMX6SX_CLK_CAN_SEL 59
#define IMX6SX_CLK_UART_SEL 60
#define IMX6SX_CLK_QSPI2_SEL 61
#define IMX6SX_CLK_LDB_DI1_SEL 62
#define IMX6SX_CLK_LDB_DI0_SEL 63
#define IMX6SX_CLK_SPDIF_SEL 64
#define IMX6SX_CLK_AUDIO_SEL 65
#define IMX6SX_CLK_ENET_PRE_SEL 66
#define IMX6SX_CLK_ENET_SEL 67
#define IMX6SX_CLK_M4_PRE_SEL 68
#define IMX6SX_CLK_M4_SEL 69
#define IMX6SX_CLK_ECSPI_SEL 70
#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
#define IMX6SX_CLK_LCDIF1_SEL 73
#define IMX6SX_CLK_LCDIF2_SEL 74
#define IMX6SX_CLK_DISPLAY_SEL 75
#define IMX6SX_CLK_CSI_SEL 76
#define IMX6SX_CLK_CKO1_SEL 77
#define IMX6SX_CLK_CKO2_SEL 78
#define IMX6SX_CLK_CKO 79
#define IMX6SX_CLK_PERIPH_CLK2 80
#define IMX6SX_CLK_PERIPH2_CLK2 81
#define IMX6SX_CLK_IPG 82
#define IMX6SX_CLK_GPU_CORE_PODF 83
#define IMX6SX_CLK_GPU_AXI_PODF 84
#define IMX6SX_CLK_LCDIF1_PODF 85
#define IMX6SX_CLK_QSPI1_PODF 86
#define IMX6SX_CLK_EIM_SLOW_PODF 87
#define IMX6SX_CLK_LCDIF2_PODF 88
#define IMX6SX_CLK_PERCLK 89
#define IMX6SX_CLK_VID_PODF 90
#define IMX6SX_CLK_CAN_PODF 91
#define IMX6SX_CLK_USDHC1_PODF 92
#define IMX6SX_CLK_USDHC2_PODF 93
#define IMX6SX_CLK_USDHC3_PODF 94
#define IMX6SX_CLK_USDHC4_PODF 95
#define IMX6SX_CLK_UART_PODF 96
#define IMX6SX_CLK_ESAI_PRED 97
#define IMX6SX_CLK_ESAI_PODF 98
#define IMX6SX_CLK_SSI3_PRED 99
#define IMX6SX_CLK_SSI3_PODF 100
#define IMX6SX_CLK_SSI1_PRED 101
#define IMX6SX_CLK_SSI1_PODF 102
#define IMX6SX_CLK_QSPI2_PRED 103
#define IMX6SX_CLK_QSPI2_PODF 104
#define IMX6SX_CLK_SSI2_PRED 105
#define IMX6SX_CLK_SSI2_PODF 106
#define IMX6SX_CLK_SPDIF_PRED 107
#define IMX6SX_CLK_SPDIF_PODF 108
#define IMX6SX_CLK_AUDIO_PRED 109
#define IMX6SX_CLK_AUDIO_PODF 110
#define IMX6SX_CLK_ENET_PODF 111
#define IMX6SX_CLK_M4_PODF 112
#define IMX6SX_CLK_ECSPI_PODF 113
#define IMX6SX_CLK_LCDIF1_PRED 114
#define IMX6SX_CLK_LCDIF2_PRED 115
#define IMX6SX_CLK_DISPLAY_PODF 116
#define IMX6SX_CLK_CSI_PODF 117
#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
#define IMX6SX_CLK_LDB_DI0_DIV_7 119
#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
#define IMX6SX_CLK_LDB_DI1_DIV_7 121
#define IMX6SX_CLK_CKO1_PODF 122
#define IMX6SX_CLK_CKO2_PODF 123
#define IMX6SX_CLK_PERIPH 124
#define IMX6SX_CLK_PERIPH2 125
#define IMX6SX_CLK_OCRAM 126
#define IMX6SX_CLK_AHB 127
#define IMX6SX_CLK_MMDC_PODF 128
#define IMX6SX_CLK_ARM 129
#define IMX6SX_CLK_AIPS_TZ1 130
#define IMX6SX_CLK_AIPS_TZ2 131
#define IMX6SX_CLK_APBH_DMA 132
#define IMX6SX_CLK_ASRC_GATE 133
#define IMX6SX_CLK_CAAM_MEM 134
#define IMX6SX_CLK_CAAM_ACLK 135
#define IMX6SX_CLK_CAAM_IPG 136
#define IMX6SX_CLK_CAN1_IPG 137
#define IMX6SX_CLK_CAN1_SERIAL 138
#define IMX6SX_CLK_CAN2_IPG 139
#define IMX6SX_CLK_CAN2_SERIAL 140
#define IMX6SX_CLK_CPU_DEBUG 141
#define IMX6SX_CLK_DCIC1 142
#define IMX6SX_CLK_DCIC2 143
#define IMX6SX_CLK_AIPS_TZ3 144
#define IMX6SX_CLK_ECSPI1 145
#define IMX6SX_CLK_ECSPI2 146
#define IMX6SX_CLK_ECSPI3 147
#define IMX6SX_CLK_ECSPI4 148
#define IMX6SX_CLK_ECSPI5 149
#define IMX6SX_CLK_EPIT1 150
#define IMX6SX_CLK_EPIT2 151
#define IMX6SX_CLK_ESAI_EXTAL 152
#define IMX6SX_CLK_WAKEUP 153
#define IMX6SX_CLK_GPT_BUS 154
#define IMX6SX_CLK_GPT_SERIAL 155
#define IMX6SX_CLK_GPU 156
#define IMX6SX_CLK_OCRAM_S 157
#define IMX6SX_CLK_CANFD 158
#define IMX6SX_CLK_CSI 159
#define IMX6SX_CLK_I2C1 160
#define IMX6SX_CLK_I2C2 161
#define IMX6SX_CLK_I2C3 162
#define IMX6SX_CLK_OCOTP 163
#define IMX6SX_CLK_IOMUXC 164
#define IMX6SX_CLK_IPMUX1 165
#define IMX6SX_CLK_IPMUX2 166
#define IMX6SX_CLK_IPMUX3 167
#define IMX6SX_CLK_TZASC1 168
#define IMX6SX_CLK_LCDIF_APB 169
#define IMX6SX_CLK_PXP_AXI 170
#define IMX6SX_CLK_M4 171
#define IMX6SX_CLK_ENET 172
#define IMX6SX_CLK_DISPLAY_AXI 173
#define IMX6SX_CLK_LCDIF2_PIX 174
#define IMX6SX_CLK_LCDIF1_PIX 175
#define IMX6SX_CLK_LDB_DI0 176
#define IMX6SX_CLK_QSPI1 177
#define IMX6SX_CLK_MLB 178
#define IMX6SX_CLK_MMDC_P0_FAST 179
#define IMX6SX_CLK_MMDC_P0_IPG 180
#define IMX6SX_CLK_AXI 181
#define IMX6SX_CLK_PCIE_AXI 182
#define IMX6SX_CLK_QSPI2 183
#define IMX6SX_CLK_PER1_BCH 184
#define IMX6SX_CLK_PER2_MAIN 185
#define IMX6SX_CLK_PWM1 186
#define IMX6SX_CLK_PWM2 187
#define IMX6SX_CLK_PWM3 188
#define IMX6SX_CLK_PWM4 189
#define IMX6SX_CLK_GPMI_BCH_APB 190
#define IMX6SX_CLK_GPMI_BCH 191
#define IMX6SX_CLK_GPMI_IO 192
#define IMX6SX_CLK_GPMI_APB 193
#define IMX6SX_CLK_ROM 194
#define IMX6SX_CLK_SDMA 195
#define IMX6SX_CLK_SPBA 196
#define IMX6SX_CLK_SPDIF 197
#define IMX6SX_CLK_SSI1_IPG 198
#define IMX6SX_CLK_SSI2_IPG 199
#define IMX6SX_CLK_SSI3_IPG 200
#define IMX6SX_CLK_SSI1 201
#define IMX6SX_CLK_SSI2 202
#define IMX6SX_CLK_SSI3 203
#define IMX6SX_CLK_UART_IPG 204
#define IMX6SX_CLK_UART_SERIAL 205
#define IMX6SX_CLK_SAI1 206
#define IMX6SX_CLK_SAI2 207
#define IMX6SX_CLK_USBOH3 208
#define IMX6SX_CLK_USDHC1 209
#define IMX6SX_CLK_USDHC2 210
#define IMX6SX_CLK_USDHC3 211
#define IMX6SX_CLK_USDHC4 212
#define IMX6SX_CLK_EIM_SLOW 213
#define IMX6SX_CLK_PWM8 214
#define IMX6SX_CLK_VADC 215
#define IMX6SX_CLK_GIS 216
#define IMX6SX_CLK_I2C4 217
#define IMX6SX_CLK_PWM5 218
#define IMX6SX_CLK_PWM6 219
#define IMX6SX_CLK_PWM7 220
#define IMX6SX_CLK_CKO1 221
#define IMX6SX_CLK_CKO2 222
#define IMX6SX_CLK_IPP_DI0 223
#define IMX6SX_CLK_IPP_DI1 224
#define IMX6SX_CLK_ENET_AHB 225
#define IMX6SX_CLK_OCRAM_PODF 226
#define IMX6SX_CLK_GPT_3M 227
#define IMX6SX_CLK_ENET_PTP 228
#define IMX6SX_CLK_ENET_PTP_REF 229
#define IMX6SX_CLK_ENET2_REF 230
#define IMX6SX_CLK_ENET2_REF_125M 231
#define IMX6SX_CLK_AUDIO 232
#define IMX6SX_CLK_LVDS1_SEL 233
#define IMX6SX_CLK_LVDS1_OUT 234
#define IMX6SX_CLK_ASRC_IPG 235
#define IMX6SX_CLK_ASRC_MEM 236
#define IMX6SX_CLK_SAI1_IPG 237
#define IMX6SX_CLK_SAI2_IPG 238
#define IMX6SX_CLK_ESAI_IPG 239
#define IMX6SX_CLK_ESAI_MEM 240
#define IMX6SX_CLK_CLK_END 241
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

36
include/dt-bindings/clock/lsi,axm5516-clks.h Normal file
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@@ -0,0 +1,36 @@
/*
* Copyright (c) 2014 LSI Corporation
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*/
#ifndef _DT_BINDINGS_CLK_AXM5516_H
#define _DT_BINDINGS_CLK_AXM5516_H
#define AXXIA_CLK_FAB_PLL 0
#define AXXIA_CLK_CPU_PLL 1
#define AXXIA_CLK_SYS_PLL 2
#define AXXIA_CLK_SM0_PLL 3
#define AXXIA_CLK_SM1_PLL 4
#define AXXIA_CLK_FAB_DIV 5
#define AXXIA_CLK_SYS_DIV 6
#define AXXIA_CLK_NRCP_DIV 7
#define AXXIA_CLK_CPU0_DIV 8
#define AXXIA_CLK_CPU1_DIV 9
#define AXXIA_CLK_CPU2_DIV 10
#define AXXIA_CLK_CPU3_DIV 11
#define AXXIA_CLK_PER_DIV 12
#define AXXIA_CLK_MMC_DIV 13
#define AXXIA_CLK_FAB 14
#define AXXIA_CLK_SYS 15
#define AXXIA_CLK_NRCP 16
#define AXXIA_CLK_CPU0 17
#define AXXIA_CLK_CPU1 18
#define AXXIA_CLK_CPU2 19
#define AXXIA_CLK_CPU3 20
#define AXXIA_CLK_PER 21
#define AXXIA_CLK_MMC 22
#endif

7
include/dt-bindings/clock/qcom,gcc-msm8960.h
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@@ -51,7 +51,7 @@
#define QDSS_TSCTR_CLK 34
#define SFAB_ADM0_M0_A_CLK 35
#define SFAB_ADM0_M1_A_CLK 36
#define SFAB_ADM0_M2_A_CLK 37
#define SFAB_ADM0_M2_H_CLK 37
#define ADM0_CLK 38
#define ADM0_PBUS_CLK 39
#define MSS_XPU_CLK 40
@@ -99,7 +99,7 @@
#define CFPB2_H_CLK 82
#define SFAB_CFPB_M_H_CLK 83
#define CFPB_MASTER_H_CLK 84
#define SFAB_CFPB_S_HCLK 85
#define SFAB_CFPB_S_H_CLK 85
#define CFPB_SPLITTER_H_CLK 86
#define TSIF_H_CLK 87
#define TSIF_INACTIVITY_TIMERS_CLK 88
@@ -110,7 +110,6 @@
#define CE1_SLEEP_CLK 93
#define CE2_H_CLK 94
#define CE2_CORE_CLK 95
#define CE2_SLEEP_CLK 96
#define SFPB_H_CLK_SRC 97
#define SFPB_H_CLK 98
#define SFAB_SFPB_M_H_CLK 99
@@ -252,7 +251,7 @@
#define MSS_S_H_CLK 235
#define MSS_CXO_SRC_CLK 236
#define SATA_H_CLK 237
#define SATA_SRC_CLK 238
#define SATA_CLK_SRC 238
#define SATA_RXOOB_CLK 239
#define SATA_PMALIVE_CLK 240
#define SATA_PHY_REF_CLK 241

4
include/dt-bindings/clock/qcom,gcc-msm8974.h
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@@ -316,5 +316,9 @@
#define GCC_CE2_CLK_SLEEP_ENA 299
#define GCC_CE2_AXI_CLK_SLEEP_ENA 300
#define GCC_CE2_AHB_CLK_SLEEP_ENA 301
#define GPLL4 302
#define GPLL4_VOTE 303
#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304
#define GCC_SDCC1_CDCCAL_FF_CLK 305
#endif

41
include/dt-bindings/clock/r7s72100-clock.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (C) 2014 Renesas Solutions Corp.
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
#define __DT_BINDINGS_CLOCK_R7S72100_H__
#define R7S72100_CLK_PLL 0
/* MSTP3 */
#define R7S72100_CLK_MTU2 3
/* MSTP4 */
#define R7S72100_CLK_SCIF0 7
#define R7S72100_CLK_SCIF1 6
#define R7S72100_CLK_SCIF2 5
#define R7S72100_CLK_SCIF3 4
#define R7S72100_CLK_SCIF4 3
#define R7S72100_CLK_SCIF5 2
#define R7S72100_CLK_SCIF6 1
#define R7S72100_CLK_SCIF7 0
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6
#define R7S72100_CLK_I2C2 5
#define R7S72100_CLK_I2C3 4
/* MSTP10 */
#define R7S72100_CLK_SPI0 7
#define R7S72100_CLK_SPI1 6
#define R7S72100_CLK_SPI2 5
#define R7S72100_CLK_SPI3 4
#define R7S72100_CLK_SPI4 3
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */

64
include/dt-bindings/clock/r8a7779-clock.h Normal file
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@@ -0,0 +1,64 @@
/*
* Copyright (C) 2013 Horms Solutions Ltd.
*
* Contact: Simon Horman <horms@verge.net.au>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
#define __DT_BINDINGS_CLOCK_R8A7779_H__
/* CPG */
#define R8A7779_CLK_PLLA 0
#define R8A7779_CLK_Z 1
#define R8A7779_CLK_ZS 2
#define R8A7779_CLK_S 3
#define R8A7779_CLK_S1 4
#define R8A7779_CLK_P 5
#define R8A7779_CLK_B 6
#define R8A7779_CLK_OUT 7
/* MSTP 0 */
#define R8A7779_CLK_HSPI 7
#define R8A7779_CLK_TMU2 14
#define R8A7779_CLK_TMU1 15
#define R8A7779_CLK_TMU0 16
#define R8A7779_CLK_HSCIF1 18
#define R8A7779_CLK_HSCIF0 19
#define R8A7779_CLK_SCIF5 21
#define R8A7779_CLK_SCIF4 22
#define R8A7779_CLK_SCIF3 23
#define R8A7779_CLK_SCIF2 24
#define R8A7779_CLK_SCIF1 25
#define R8A7779_CLK_SCIF0 26
#define R8A7779_CLK_I2C3 27
#define R8A7779_CLK_I2C2 28
#define R8A7779_CLK_I2C1 29
#define R8A7779_CLK_I2C0 30
/* MSTP 1 */
#define R8A7779_CLK_USB01 0
#define R8A7779_CLK_USB2 1
#define R8A7779_CLK_DU 3
#define R8A7779_CLK_VIN2 8
#define R8A7779_CLK_VIN1 9
#define R8A7779_CLK_VIN0 10
#define R8A7779_CLK_ETHER 14
#define R8A7779_CLK_SATA 15
#define R8A7779_CLK_PCIE 16
#define R8A7779_CLK_VIN3 20
/* MSTP 3 */
#define R8A7779_CLK_SDHI3 20
#define R8A7779_CLK_SDHI2 21
#define R8A7779_CLK_SDHI1 22
#define R8A7779_CLK_SDHI0 23
#define R8A7779_CLK_MMC1 30
#define R8A7779_CLK_MMC0 31
#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */

7
include/dt-bindings/clock/r8a7790-clock.h
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@@ -33,8 +33,8 @@
#define R8A7790_CLK_TMU0 25
#define R8A7790_CLK_VSP1_DU1 27
#define R8A7790_CLK_VSP1_DU0 28
#define R8A7790_CLK_VSP1_RT 30
#define R8A7790_CLK_VSP1_SY 31
#define R8A7790_CLK_VSP1_R 30
#define R8A7790_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7790_CLK_SCIFA2 2
@@ -50,6 +50,7 @@
#define R8A7790_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7790_CLK_IIC2 0
#define R8A7790_CLK_TPU0 4
#define R8A7790_CLK_MMCIF1 5
#define R8A7790_CLK_SDHI3 11
@@ -57,6 +58,8 @@
#define R8A7790_CLK_SDHI1 13
#define R8A7790_CLK_SDHI0 14
#define R8A7790_CLK_MMCIF0 15
#define R8A7790_CLK_IIC0 18
#define R8A7790_CLK_IIC1 23
#define R8A7790_CLK_SSUSB 28
#define R8A7790_CLK_CMT1 29
#define R8A7790_CLK_USBDMAC0 30

8
include/dt-bindings/clock/r8a7791-clock.h
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@@ -32,7 +32,7 @@
#define R8A7791_CLK_TMU0 25
#define R8A7791_CLK_VSP1_DU1 27
#define R8A7791_CLK_VSP1_DU0 28
#define R8A7791_CLK_VSP1_SY 31
#define R8A7791_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7791_CLK_SCIFA2 2
@@ -43,7 +43,8 @@
#define R8A7791_CLK_SCIFB1 7
#define R8A7791_CLK_MSIOF1 8
#define R8A7791_CLK_SCIFB2 16
#define R8A7791_CLK_DMAC 18
#define R8A7791_CLK_SYS_DMAC1 18
#define R8A7791_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7791_CLK_TPU0 4
@@ -51,6 +52,8 @@
#define R8A7791_CLK_SDHI1 12
#define R8A7791_CLK_SDHI0 14
#define R8A7791_CLK_MMCIF0 15
#define R8A7791_CLK_IIC0 18
#define R8A7791_CLK_IIC1 23
#define R8A7791_CLK_SSUSB 28
#define R8A7791_CLK_CMT1 29
#define R8A7791_CLK_USBDMAC0 30
@@ -61,6 +64,7 @@
#define R8A7791_CLK_PWM 23
/* MSTP7 */
#define R8A7791_CLK_EHCI 3
#define R8A7791_CLK_HSUSB 4
#define R8A7791_CLK_HSCIF2 13
#define R8A7791_CLK_SCIF5 14

62
include/dt-bindings/clock/s3c2410.h Normal file
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@@ -0,0 +1,62 @@
/*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clock controllers of Samsung S3C2410 and later.
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
/*
* Let each exported clock get a unique index, which is used on DT-enabled
* platforms to lookup the clock from a clock specifier. These indices are
* therefore considered an ABI and so must not be changed. This implies
* that new clocks should be added either in free spaces between clock groups
* or at the end.
*/
/* Core clocks. */
/* id 1 is reserved */
#define MPLL 2
#define UPLL 3
#define FCLK 4
#define HCLK 5
#define PCLK 6
#define UCLK 7
#define ARMCLK 8
/* pclk-gates */
#define PCLK_UART0 16
#define PCLK_UART1 17
#define PCLK_UART2 18
#define PCLK_I2C 19
#define PCLK_SDI 20
#define PCLK_SPI 21
#define PCLK_ADC 22
#define PCLK_AC97 23
#define PCLK_I2S 24
#define PCLK_PWM 25
#define PCLK_RTC 26
#define PCLK_GPIO 27
/* hclk-gates */
#define HCLK_LCD 32
#define HCLK_USBH 33
#define HCLK_USBD 34
#define HCLK_NAND 35
#define HCLK_CAM 36
#define CAMIF 40
/* Total number of clocks. */
#define NR_CLKS (CAMIF + 1)
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */

73
include/dt-bindings/clock/s3c2412.h Normal file
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@@ -0,0 +1,73 @@
/*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clock controllers of Samsung S3C2412.
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
/*
* Let each exported clock get a unique index, which is used on DT-enabled
* platforms to lookup the clock from a clock specifier. These indices are
* therefore considered an ABI and so must not be changed. This implies
* that new clocks should be added either in free spaces between clock groups
* or at the end.
*/
/* Core clocks. */
/* id 1 is reserved */
#define MPLL 2
#define UPLL 3
#define MDIVCLK 4
#define MSYSCLK 5
#define USYSCLK 6
#define HCLK 7
#define PCLK 8
#define ARMDIV 9
#define ARMCLK 10
/* Special clocks */
#define SCLK_CAM 16
#define SCLK_UART 17
#define SCLK_I2S 18
#define SCLK_USBD 19
#define SCLK_USBH 20
/* pclk-gates */
#define PCLK_WDT 32
#define PCLK_SPI 33
#define PCLK_I2S 34
#define PCLK_I2C 35
#define PCLK_ADC 36
#define PCLK_RTC 37
#define PCLK_GPIO 38
#define PCLK_UART2 39
#define PCLK_UART1 40
#define PCLK_UART0 41
#define PCLK_SDI 42
#define PCLK_PWM 43
#define PCLK_USBD 44
/* hclk-gates */
#define HCLK_HALF 48
#define HCLK_X2 49
#define HCLK_SDRAM 50
#define HCLK_USBH 51
#define HCLK_LCD 52
#define HCLK_NAND 53
#define HCLK_DMA3 54
#define HCLK_DMA2 55
#define HCLK_DMA1 56
#define HCLK_DMA0 57
/* Total number of clocks. */
#define NR_CLKS (HCLK_DMA0 + 1)
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */

92
include/dt-bindings/clock/s3c2443.h Normal file
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@@ -0,0 +1,92 @@
/*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clock controllers of Samsung S3C2443 and later.
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
/*
* Let each exported clock get a unique index, which is used on DT-enabled
* platforms to lookup the clock from a clock specifier. These indices are
* therefore considered an ABI and so must not be changed. This implies
* that new clocks should be added either in free spaces between clock groups
* or at the end.
*/
/* Core clocks. */
#define MSYSCLK 1
#define ESYSCLK 2
#define ARMDIV 3
#define ARMCLK 4
#define HCLK 5
#define PCLK 6
/* Special clocks */
#define SCLK_HSSPI0 16
#define SCLK_FIMD 17
#define SCLK_I2S0 18
#define SCLK_I2S1 19
#define SCLK_HSMMC1 20
#define SCLK_HSMMC_EXT 21
#define SCLK_CAM 22
#define SCLK_UART 23
#define SCLK_USBH 24
/* Muxes */
#define MUX_HSSPI0 32
#define MUX_HSSPI1 33
#define MUX_HSMMC0 34
#define MUX_HSMMC1 35
/* hclk-gates */
#define HCLK_DMA0 48
#define HCLK_DMA1 49
#define HCLK_DMA2 50
#define HCLK_DMA3 51
#define HCLK_DMA4 52
#define HCLK_DMA5 53
#define HCLK_DMA6 54
#define HCLK_DMA7 55
#define HCLK_CAM 56
#define HCLK_LCD 57
#define HCLK_USBH 58
#define HCLK_USBD 59
#define HCLK_IROM 60
#define HCLK_HSMMC0 61
#define HCLK_HSMMC1 62
#define HCLK_CFC 63
#define HCLK_SSMC 64
#define HCLK_DRAM 65
#define HCLK_2D 66
/* pclk-gates */
#define PCLK_UART0 72
#define PCLK_UART1 73
#define PCLK_UART2 74
#define PCLK_UART3 75
#define PCLK_I2C0 76
#define PCLK_SDI 77
#define PCLK_SPI0 78
#define PCLK_ADC 79
#define PCLK_AC97 80
#define PCLK_I2S0 81
#define PCLK_PWM 82
#define PCLK_WDT 83
#define PCLK_RTC 84
#define PCLK_GPIO 85
#define PCLK_SPI1 86
#define PCLK_CHIPID 87
#define PCLK_I2C1 88
#define PCLK_I2S1 89
#define PCLK_PCM 90
/* Total number of clocks. */
#define NR_CLKS (PCLK_PCM + 1)
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */

16
include/dt-bindings/clock/stih415-clks.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH415 SoC.
*/
#ifndef _CLK_STIH415
#define _CLK_STIH415
/* CLOCKGEN A0 */
#define CLK_ICN_REG 0
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_ICN_IF_2 0
#define CLK_GMAC0_PHY 3
#endif

16
include/dt-bindings/clock/stih416-clks.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH416 SoC.
*/
#ifndef _CLK_STIH416
#define _CLK_STIH416
/* CLOCKGEN A0 */
#define CLK_ICN_REG 0
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_ICN_IF_2 0
#define CLK_GMAC0_PHY 3
#endif

3
include/dt-bindings/clock/tegra114-car.h
View File

@@ -337,6 +337,7 @@
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_CLK_MAX 311
#define TEGRA114_CLK_XUSB_SS_DIV2 311
#define TEGRA114_CLK_CLK_MAX 312
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */

3
include/dt-bindings/clock/tegra124-car.h
View File

@@ -336,6 +336,7 @@
#define TEGRA124_CLK_DSIA_MUX 309
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_CLK_MAX 312
#define TEGRA124_CLK_XUSB_SS_DIV2 312
#define TEGRA124_CLK_CLK_MAX 313
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */

25
include/dt-bindings/pinctrl/omap.h
View File

@@ -62,12 +62,29 @@
#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define OMAP4_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0040) (val)
#define OMAP4_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xe040) (val)
#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define OMAP5_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2840) (val)
#define OMAP5_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xc840) (val)
#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
/*
* Macros to allow using the offset from the padconf physical address
* instead of the offset from padconf base.
*/
#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/*
* Define some commonly used pins configured by the boards.
* Note that some boards use alternative pins, so check
* the schematics before using these.
*/
#define OMAP3_UART1_RX 0x152
#define OMAP3_UART2_RX 0x14a
#define OMAP3_UART3_RX 0x16e
#define OMAP4_UART2_RX 0xdc
#define OMAP4_UART3_RX 0x104
#define OMAP4_UART4_RX 0x11c
#endif

1
include/dt-bindings/reset-controller/stih415-resets.h
View File

@@ -22,5 +22,6 @@
#define STIH415_USB0_SOFTRESET 3
#define STIH415_USB1_SOFTRESET 4
#define STIH415_USB2_SOFTRESET 5
#define STIH415_KEYSCAN_SOFTRESET 6
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */

1
include/dt-bindings/reset-controller/stih416-resets.h
View File

@@ -46,5 +46,6 @@
#define STIH416_COMPO_A_SOFTRESET 25
#define STIH416_VP8_DEC_SOFTRESET 26
#define STIH416_VTG_MAIN_SOFTRESET 27
#define STIH416_KEYSCAN_SOFTRESET 28
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */

90
include/dt-bindings/reset/altr,rst-mgr.h Normal file
View File

@@ -0,0 +1,90 @@
/*
* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
/* MPUMODRST */
#define CPU0_RESET 0
#define CPU1_RESET 1
#define WDS_RESET 2
#define SCUPER_RESET 3
#define L2_RESET 4
/* PERMODRST */
#define EMAC0_RESET 32
#define EMAC1_RESET 33
#define USB0_RESET 34
#define USB1_RESET 35
#define NAND_RESET 36
#define QSPI_RESET 37
#define L4WD0_RESET 38
#define L4WD1_RESET 39
#define OSC1TIMER0_RESET 40
#define OSC1TIMER1_RESET 41
#define SPTIMER0_RESET 42
#define SPTIMER1_RESET 43
#define I2C0_RESET 44
#define I2C1_RESET 45
#define I2C2_RESET 46
#define I2C3_RESET 47
#define UART0_RESET 48
#define UART1_RESET 49
#define SPIM0_RESET 50
#define SPIM1_RESET 51
#define SPIS0_RESET 52
#define SPIS1_RESET 53
#define SDMMC_RESET 54
#define CAN0_RESET 55
#define CAN1_RESET 56
#define GPIO0_RESET 57
#define GPIO1_RESET 58
#define GPIO2_RESET 59
#define DMA_RESET 60
#define SDR_RESET 61
/* PER2MODRST */
#define DMAIF0_RESET 64
#define DMAIF1_RESET 65
#define DMAIF2_RESET 66
#define DMAIF3_RESET 67
#define DMAIF4_RESET 68
#define DMAIF5_RESET 69
#define DMAIF6_RESET 70
#define DMAIF7_RESET 71
/* BRGMODRST */
#define HPS2FPGA_RESET 96
#define LWHPS2FPGA_RESET 97
#define FPGA2HPS_RESET 98
/* MISCMODRST*/
#define ROM_RESET 128
#define OCRAM_RESET 129
#define SYSMGR_RESET 130
#define SYSMGRCOLD_RESET 131
#define FPGAMGR_RESET 132
#define ACPIDMAP_RESET 133
#define S2F_RESET 134
#define S2FCOLD_RESET 135
#define NRSTPIN_RESET 136
#define TIMESTAMPCOLD_RESET 137
#define CLKMGRCOLD_RESET 138
#define SCANMGR_RESET 139
#define FRZCTRLCOLD_RESET 140
#define SYSDBG_RESET 141
#define DBG_RESET 142
#define TAPCOLD_RESET 143
#define SDRCOLD_RESET 144
#endif

2
include/dt-bindings/reset/qcom,gcc-msm8960.h
View File

@@ -58,7 +58,7 @@
#define PPSS_PROC_RESET 41
#define PPSS_RESET 42
#define DMA_BAM_RESET 43
#define SIC_TIC_RESET 44
#define SPS_TIC_H_RESET 44
#define SLIMBUS_H_RESET 45
#define SFAB_CFPB_M_RESET 46
#define SFAB_CFPB_S_RESET 47

26
include/dt-bindings/soc/qcom,gsbi.h Normal file
View File

@@ -0,0 +1,26 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_QCOM_GSBI_H
#define __DT_BINDINGS_QCOM_GSBI_H
#define GSBI_PROT_IDLE 0
#define GSBI_PROT_I2C_UIM 1
#define GSBI_PROT_I2C 2
#define GSBI_PROT_SPI 3
#define GSBI_PROT_UART_W_FC 4
#define GSBI_PROT_UIM 5
#define GSBI_PROT_I2C_UART 6
#define GSBI_CRCI_QUP 0
#define GSBI_CRCI_UART 1
#endif

1
include/linux/ahci_platform.h
View File

@@ -44,6 +44,7 @@ struct ahci_host_priv *ahci_platform_get_resources(
int ahci_platform_init_host(struct platform_device *pdev,
struct ahci_host_priv *hpriv,
const struct ata_port_info *pi_template,
unsigned long host_flags,
unsigned int force_port_map,
unsigned int mask_port_map);

42
include/linux/amba/mmci.h
View File

@@ -6,28 +6,9 @@
#include <linux/mmc/host.h>
/*
* These defines is places here due to access is needed from machine
* configuration files. The ST Micro version does not have ROD and
* reuse the voltage registers for direction settings.
*/
#define MCI_ST_DATA2DIREN (1 << 2)
#define MCI_ST_CMDDIREN (1 << 3)
#define MCI_ST_DATA0DIREN (1 << 4)
#define MCI_ST_DATA31DIREN (1 << 5)
#define MCI_ST_FBCLKEN (1 << 7)
#define MCI_ST_DATA74DIREN (1 << 8)
/* Just some dummy forwarding */
struct dma_chan;
/**
* struct mmci_platform_data - platform configuration for the MMCI
* (also known as PL180) block.
* @f_max: the maximum operational frequency for this host in this
* platform configuration. When this is specified it takes precedence
* over the module parameter for the same frequency.
* @ocr_mask: available voltages on the 4 pins from the block, this
* is ignored if a regulator is used, see the MMC_VDD_* masks in
* mmc/host.h
@@ -42,37 +23,14 @@ struct dma_chan;
* @gpio_wp: read this GPIO pin to see if the card is write protected
* @gpio_cd: read this GPIO pin to detect card insertion
* @cd_invert: true if the gpio_cd pin value is active low
* @capabilities: the capabilities of the block as implemented in
* this platform, signify anything MMC_CAP_* from mmc/host.h
* @capabilities2: more capabilities, MMC_CAP2_* from mmc/host.h
* @sigdir: a bit field indicating for what bits in the MMC bus the host
* should enable signal direction indication.
* @dma_filter: function used to select an appropriate RX and TX
* DMA channel to be used for DMA, if and only if you're deploying the
* generic DMA engine
* @dma_rx_param: parameter passed to the DMA allocation
* filter in order to select an appropriate RX channel. If
* there is a bidirectional RX+TX channel, then just specify
* this and leave dma_tx_param set to NULL
* @dma_tx_param: parameter passed to the DMA allocation
* filter in order to select an appropriate TX channel. If this
* is NULL the driver will attempt to use the RX channel as a
* bidirectional channel
*/
struct mmci_platform_data {
unsigned int f_max;
unsigned int ocr_mask;
int (*ios_handler)(struct device *, struct mmc_ios *);
unsigned int (*status)(struct device *);
int gpio_wp;
int gpio_cd;
bool cd_invert;
unsigned long capabilities;
unsigned long capabilities2;
u32 sigdir;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
void *dma_rx_param;
void *dma_tx_param;
};
#endif

47
include/linux/amba/xilinx_dma.h Normal file
View File

@@ -0,0 +1,47 @@
/*
* Xilinx DMA Engine drivers support header file
*
* Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DMA_XILINX_DMA_H
#define __DMA_XILINX_DMA_H
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
/**
* struct xilinx_vdma_config - VDMA Configuration structure
* @frm_dly: Frame delay
* @gen_lock: Whether in gen-lock mode
* @master: Master that it syncs to
* @frm_cnt_en: Enable frame count enable
* @park: Whether wants to park
* @park_frm: Frame to park on
* @coalesc: Interrupt coalescing threshold
* @delay: Delay counter
* @reset: Reset Channel
* @ext_fsync: External Frame Sync source
*/
struct xilinx_vdma_config {
int frm_dly;
int gen_lock;
int master;
int frm_cnt_en;
int park;
int park_frm;
int coalesc;
int delay;
int reset;
int ext_fsync;
};
int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
struct xilinx_vdma_config *cfg);
#endif

2
include/linux/ath9k_platform.h
View File

@@ -36,6 +36,8 @@ struct ath9k_platform_data {
int (*get_mac_revision)(void);
int (*external_reset)(void);
bool use_eeprom;
};
#endif /* _LINUX_ATH9K_PLATFORM_H */

36
include/linux/atomic.h
View File

@@ -3,6 +3,42 @@
#define _LINUX_ATOMIC_H
#include <asm/atomic.h>
/*
* Provide __deprecated wrappers for the new interface, avoid flag day changes.
* We need the ugly external functions to break header recursion hell.
*/
#ifndef smp_mb__before_atomic_inc
static inline void __deprecated smp_mb__before_atomic_inc(void)
{
extern void __smp_mb__before_atomic(void);
__smp_mb__before_atomic();
}
#endif
#ifndef smp_mb__after_atomic_inc
static inline void __deprecated smp_mb__after_atomic_inc(void)
{
extern void __smp_mb__after_atomic(void);
__smp_mb__after_atomic();
}
#endif
#ifndef smp_mb__before_atomic_dec
static inline void __deprecated smp_mb__before_atomic_dec(void)
{
extern void __smp_mb__before_atomic(void);
__smp_mb__before_atomic();
}
#endif
#ifndef smp_mb__after_atomic_dec
static inline void __deprecated smp_mb__after_atomic_dec(void)
{
extern void __smp_mb__after_atomic(void);
__smp_mb__after_atomic();
}
#endif
/**
* atomic_add_unless - add unless the number is already a given value
* @v: pointer of type atomic_t

15
include/linux/bio.h
View File

@@ -186,6 +186,15 @@ static inline void *bio_data(struct bio *bio)
#define BIOVEC_SEG_BOUNDARY(q, b1, b2) \
__BIO_SEG_BOUNDARY(bvec_to_phys((b1)), bvec_to_phys((b2)) + (b2)->bv_len, queue_segment_boundary((q)))
/*
* Check if adding a bio_vec after bprv with offset would create a gap in
* the SG list. Most drivers don't care about this, but some do.
*/
static inline bool bvec_gap_to_prev(struct bio_vec *bprv, unsigned int offset)
{
return offset || ((bprv->bv_offset + bprv->bv_len) & (PAGE_SIZE - 1));
}
#define bio_io_error(bio) bio_endio((bio), -EIO)
/*
@@ -333,7 +342,7 @@ static inline struct bio *bio_next_split(struct bio *bio, int sectors,
extern struct bio_set *bioset_create(unsigned int, unsigned int);
extern void bioset_free(struct bio_set *);
extern mempool_t *biovec_create_pool(struct bio_set *bs, int pool_entries);
extern mempool_t *biovec_create_pool(int pool_entries);
extern struct bio *bio_alloc_bioset(gfp_t, int, struct bio_set *);
extern void bio_put(struct bio *);
@@ -644,10 +653,6 @@ struct biovec_slab {
#if defined(CONFIG_BLK_DEV_INTEGRITY)
#define bip_vec_idx(bip, idx) (&(bip->bip_vec[(idx)]))
#define bip_for_each_vec(bvl, bip, iter) \
for_each_bvec(bvl, (bip)->bip_vec, iter, (bip)->bip_iter)

20
include/linux/bitops.h
View File

@@ -32,6 +32,26 @@ extern unsigned long __sw_hweight64(__u64 w);
*/
#include <asm/bitops.h>
/*
* Provide __deprecated wrappers for the new interface, avoid flag day changes.
* We need the ugly external functions to break header recursion hell.
*/
#ifndef smp_mb__before_clear_bit
static inline void __deprecated smp_mb__before_clear_bit(void)
{
extern void __smp_mb__before_atomic(void);
__smp_mb__before_atomic();
}
#endif
#ifndef smp_mb__after_clear_bit
static inline void __deprecated smp_mb__after_clear_bit(void)
{
extern void __smp_mb__after_atomic(void);
__smp_mb__after_atomic();
}
#endif
#define for_each_set_bit(bit, addr, size) \
for ((bit) = find_first_bit((addr), (size)); \
(bit) < (size); \

103
include/linux/blk-mq.h
View File

@@ -8,7 +8,13 @@ struct blk_mq_tags;
struct blk_mq_cpu_notifier {
struct list_head list;
void *data;
void (*notify)(void *data, unsigned long action, unsigned int cpu);
int (*notify)(void *data, unsigned long action, unsigned int cpu);
};
struct blk_mq_ctxmap {
unsigned int map_size;
unsigned int bits_per_word;
struct blk_align_bitmap *map;
};
struct blk_mq_hw_ctx {
@@ -18,7 +24,11 @@ struct blk_mq_hw_ctx {
} ____cacheline_aligned_in_smp;
unsigned long state; /* BLK_MQ_S_* flags */
struct delayed_work delayed_work;
struct delayed_work run_work;
struct delayed_work delay_work;
cpumask_var_t cpumask;
int next_cpu;
int next_cpu_batch;
unsigned long flags; /* BLK_MQ_F_* flags */
@@ -27,13 +37,13 @@ struct blk_mq_hw_ctx {
void *driver_data;
struct blk_mq_ctxmap ctx_map;
unsigned int nr_ctx;
struct blk_mq_ctx **ctxs;
unsigned int nr_ctx_map;
unsigned long *ctx_map;
struct request **rqs;
struct list_head page_list;
atomic_t wait_index;
struct blk_mq_tags *tags;
unsigned long queued;
@@ -41,31 +51,40 @@ struct blk_mq_hw_ctx {
#define BLK_MQ_MAX_DISPATCH_ORDER 10
unsigned long dispatched[BLK_MQ_MAX_DISPATCH_ORDER];
unsigned int queue_depth;
unsigned int numa_node;
unsigned int cmd_size; /* per-request extra data */
atomic_t nr_active;
struct blk_mq_cpu_notifier cpu_notifier;
struct kobject kobj;
};
struct blk_mq_reg {
struct blk_mq_tag_set {
struct blk_mq_ops *ops;
unsigned int nr_hw_queues;
unsigned int queue_depth;
unsigned int queue_depth; /* max hw supported */
unsigned int reserved_tags;
unsigned int cmd_size; /* per-request extra data */
int numa_node;
unsigned int timeout;
unsigned int flags; /* BLK_MQ_F_* */
void *driver_data;
struct blk_mq_tags **tags;
struct mutex tag_list_lock;
struct list_head tag_list;
};
typedef int (queue_rq_fn)(struct blk_mq_hw_ctx *, struct request *);
typedef struct blk_mq_hw_ctx *(map_queue_fn)(struct request_queue *, const int);
typedef struct blk_mq_hw_ctx *(alloc_hctx_fn)(struct blk_mq_reg *,unsigned int);
typedef void (free_hctx_fn)(struct blk_mq_hw_ctx *, unsigned int);
typedef int (init_hctx_fn)(struct blk_mq_hw_ctx *, void *, unsigned int);
typedef void (exit_hctx_fn)(struct blk_mq_hw_ctx *, unsigned int);
typedef int (init_request_fn)(void *, struct request *, unsigned int,
unsigned int, unsigned int);
typedef void (exit_request_fn)(void *, struct request *, unsigned int,
unsigned int);
struct blk_mq_ops {
/*
@@ -85,12 +104,6 @@ struct blk_mq_ops {
softirq_done_fn *complete;
/*
* Override for hctx allocations (should probably go)
*/
alloc_hctx_fn *alloc_hctx;
free_hctx_fn *free_hctx;
/*
* Called when the block layer side of a hardware queue has been
* set up, allowing the driver to allocate/init matching structures.
@@ -98,6 +111,14 @@ struct blk_mq_ops {
*/
init_hctx_fn *init_hctx;
exit_hctx_fn *exit_hctx;
/*
* Called for every command allocated by the block layer to allow
* the driver to set up driver specific data.
* Ditto for exit/teardown.
*/
init_request_fn *init_request;
exit_request_fn *exit_request;
};
enum {
@@ -107,18 +128,24 @@ enum {
BLK_MQ_F_SHOULD_MERGE = 1 << 0,
BLK_MQ_F_SHOULD_SORT = 1 << 1,
BLK_MQ_F_SHOULD_IPI = 1 << 2,
BLK_MQ_F_TAG_SHARED = 1 << 2,
BLK_MQ_F_SG_MERGE = 1 << 3,
BLK_MQ_F_SYSFS_UP = 1 << 4,
BLK_MQ_S_STOPPED = 0,
BLK_MQ_S_TAG_ACTIVE = 1,
BLK_MQ_MAX_DEPTH = 2048,
BLK_MQ_MAX_DEPTH = 10240,
BLK_MQ_CPU_WORK_BATCH = 8,
};
struct request_queue *blk_mq_init_queue(struct blk_mq_reg *, void *);
struct request_queue *blk_mq_init_queue(struct blk_mq_tag_set *);
int blk_mq_register_disk(struct gendisk *);
void blk_mq_unregister_disk(struct gendisk *);
int blk_mq_init_commands(struct request_queue *, int (*init)(void *data, struct blk_mq_hw_ctx *, struct request *, unsigned int), void *data);
void blk_mq_free_commands(struct request_queue *, void (*free)(void *data, struct blk_mq_hw_ctx *, struct request *, unsigned int), void *data);
int blk_mq_alloc_tag_set(struct blk_mq_tag_set *set);
void blk_mq_free_tag_set(struct blk_mq_tag_set *set);
void blk_mq_flush_plug_list(struct blk_plug *plug, bool from_schedule);
@@ -126,28 +153,28 @@ void blk_mq_insert_request(struct request *, bool, bool, bool);
void blk_mq_run_queues(struct request_queue *q, bool async);
void blk_mq_free_request(struct request *rq);
bool blk_mq_can_queue(struct blk_mq_hw_ctx *);
struct request *blk_mq_alloc_request(struct request_queue *q, int rw, gfp_t gfp);
struct request *blk_mq_alloc_reserved_request(struct request_queue *q, int rw, gfp_t gfp);
struct request *blk_mq_rq_from_tag(struct request_queue *q, unsigned int tag);
struct request *blk_mq_alloc_request(struct request_queue *q, int rw,
gfp_t gfp, bool reserved);
struct request *blk_mq_tag_to_rq(struct blk_mq_tags *tags, unsigned int tag);
struct blk_mq_hw_ctx *blk_mq_map_queue(struct request_queue *, const int ctx_index);
struct blk_mq_hw_ctx *blk_mq_alloc_single_hw_queue(struct blk_mq_reg *, unsigned int);
void blk_mq_free_single_hw_queue(struct blk_mq_hw_ctx *, unsigned int);
struct blk_mq_hw_ctx *blk_mq_alloc_single_hw_queue(struct blk_mq_tag_set *, unsigned int, int);
bool blk_mq_end_io_partial(struct request *rq, int error,
unsigned int nr_bytes);
static inline void blk_mq_end_io(struct request *rq, int error)
{
bool done = !blk_mq_end_io_partial(rq, error, blk_rq_bytes(rq));
BUG_ON(!done);
}
void blk_mq_end_io(struct request *rq, int error);
void __blk_mq_end_io(struct request *rq, int error);
void blk_mq_requeue_request(struct request *rq);
void blk_mq_add_to_requeue_list(struct request *rq, bool at_head);
void blk_mq_kick_requeue_list(struct request_queue *q);
void blk_mq_complete_request(struct request *rq);
void blk_mq_stop_hw_queue(struct blk_mq_hw_ctx *hctx);
void blk_mq_start_hw_queue(struct blk_mq_hw_ctx *hctx);
void blk_mq_stop_hw_queues(struct request_queue *q);
void blk_mq_start_stopped_hw_queues(struct request_queue *q);
void blk_mq_start_hw_queues(struct request_queue *q);
void blk_mq_start_stopped_hw_queues(struct request_queue *q, bool async);
void blk_mq_delay_queue(struct blk_mq_hw_ctx *hctx, unsigned long msecs);
void blk_mq_tag_busy_iter(struct blk_mq_tags *tags, void (*fn)(void *data, unsigned long *), void *data);
/*
* Driver command data is immediately after the request. So subtract request
@@ -162,12 +189,6 @@ static inline void *blk_mq_rq_to_pdu(struct request *rq)
return (void *) rq + sizeof(*rq);
}
static inline struct request *blk_mq_tag_to_rq(struct blk_mq_hw_ctx *hctx,
unsigned int tag)
{
return hctx->rqs[tag];
}
#define queue_for_each_hw_ctx(q, hctx, i) \
for ((i) = 0; (i) < (q)->nr_hw_queues && \
({ hctx = (q)->queue_hw_ctx[i]; 1; }); (i)++)

6
include/linux/blk_types.h
View File

@@ -5,8 +5,6 @@
#ifndef __LINUX_BLK_TYPES_H
#define __LINUX_BLK_TYPES_H
#ifdef CONFIG_BLOCK
#include <linux/types.h>
struct bio_set;
@@ -28,6 +26,8 @@ struct bio_vec {
unsigned int bv_offset;
};
#ifdef CONFIG_BLOCK
struct bvec_iter {
sector_t bi_sector; /* device address in 512 byte
sectors */
@@ -190,6 +190,7 @@ enum rq_flag_bits {
__REQ_PM, /* runtime pm request */
__REQ_END, /* last of chain of requests */
__REQ_HASHED, /* on IO scheduler merge hash */
__REQ_MQ_INFLIGHT, /* track inflight for MQ */
__REQ_NR_BITS, /* stops here */
};
@@ -243,5 +244,6 @@ enum rq_flag_bits {
#define REQ_PM (1ULL << __REQ_PM)
#define REQ_END (1ULL << __REQ_END)
#define REQ_HASHED (1ULL << __REQ_HASHED)
#define REQ_MQ_INFLIGHT (1ULL << __REQ_MQ_INFLIGHT)
#endif /* __LINUX_BLK_TYPES_H */

75
include/linux/blkdev.h
View File

@@ -90,15 +90,15 @@ enum rq_cmd_type_bits {
#define BLK_MAX_CDB 16
/*
* try to put the fields that are referenced together in the same cacheline.
* if you modify this structure, be sure to check block/blk-core.c:blk_rq_init()
* as well!
* Try to put the fields that are referenced together in the same cacheline.
*
* If you modify this structure, make sure to update blk_rq_init() and
* especially blk_mq_rq_ctx_init() to take care of the added fields.
*/
struct request {
struct list_head queuelist;
union {
struct call_single_data csd;
struct work_struct mq_flush_work;
unsigned long fifo_time;
};
@@ -178,7 +178,6 @@ struct request {
unsigned short ioprio;
void *special; /* opaque pointer available for LLD use */
char *buffer; /* kaddr of the current segment if available */
int tag;
int errors;
@@ -281,6 +280,7 @@ struct queue_limits {
unsigned long seg_boundary_mask;
unsigned int max_hw_sectors;
unsigned int chunk_sectors;
unsigned int max_sectors;
unsigned int max_segment_size;
unsigned int physical_block_size;
@@ -336,7 +336,7 @@ struct request_queue {
unsigned int *mq_map;
/* sw queues */
struct blk_mq_ctx *queue_ctx;
struct blk_mq_ctx __percpu *queue_ctx;
unsigned int nr_queues;
/* hw dispatch queues */
@@ -463,6 +463,10 @@ struct request_queue {
struct request *flush_rq;
spinlock_t mq_flush_lock;
struct list_head requeue_list;
spinlock_t requeue_lock;
struct work_struct requeue_work;
struct mutex sysfs_lock;
int bypass_depth;
@@ -481,6 +485,9 @@ struct request_queue {
wait_queue_head_t mq_freeze_wq;
struct percpu_counter mq_usage_counter;
struct list_head all_q_node;
struct blk_mq_tag_set *tag_set;
struct list_head tag_set_list;
};
#define QUEUE_FLAG_QUEUED 1 /* uses generic tag queueing */
@@ -504,6 +511,8 @@ struct request_queue {
#define QUEUE_FLAG_SAME_FORCE 18 /* force complete on same CPU */
#define QUEUE_FLAG_DEAD 19 /* queue tear-down finished */
#define QUEUE_FLAG_INIT_DONE 20 /* queue is initialized */
#define QUEUE_FLAG_NO_SG_MERGE 21 /* don't attempt to merge SG segments*/
#define QUEUE_FLAG_SG_GAPS 22 /* queue doesn't support SG gaps */
#define QUEUE_FLAG_DEFAULT ((1 << QUEUE_FLAG_IO_STAT) | \
(1 << QUEUE_FLAG_STACKABLE) | \
@@ -613,6 +622,15 @@ static inline void queue_flag_clear(unsigned int flag, struct request_queue *q)
#define rq_data_dir(rq) (((rq)->cmd_flags & 1) != 0)
/*
* Driver can handle struct request, if it either has an old style
* request_fn defined, or is blk-mq based.
*/
static inline bool queue_is_rq_based(struct request_queue *q)
{
return q->request_fn || q->mq_ops;
}
static inline unsigned int blk_queue_cluster(struct request_queue *q)
{
return q->limits.cluster;
@@ -779,6 +797,7 @@ extern void __blk_put_request(struct request_queue *, struct request *);
extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
extern struct request *blk_make_request(struct request_queue *, struct bio *,
gfp_t);
extern void blk_rq_set_block_pc(struct request *);
extern void blk_requeue_request(struct request_queue *, struct request *);
extern void blk_add_request_payload(struct request *rq, struct page *page,
unsigned int len);
@@ -894,6 +913,20 @@ static inline unsigned int blk_queue_get_max_sectors(struct request_queue *q,
return q->limits.max_sectors;
}
/*
* Return maximum size of a request at given offset. Only valid for
* file system requests.
*/
static inline unsigned int blk_max_size_offset(struct request_queue *q,
sector_t offset)
{
if (!q->limits.chunk_sectors)
return q->limits.max_sectors;
return q->limits.chunk_sectors -
(offset & (q->limits.chunk_sectors - 1));
}
static inline unsigned int blk_rq_get_max_sectors(struct request *rq)
{
struct request_queue *q = rq->q;
@@ -901,7 +934,11 @@ static inline unsigned int blk_rq_get_max_sectors(struct request *rq)
if (unlikely(rq->cmd_type == REQ_TYPE_BLOCK_PC))
return q->limits.max_hw_sectors;
return blk_queue_get_max_sectors(q, rq->cmd_flags);
if (!q->limits.chunk_sectors)
return blk_queue_get_max_sectors(q, rq->cmd_flags);
return min(blk_max_size_offset(q, blk_rq_pos(rq)),
blk_queue_get_max_sectors(q, rq->cmd_flags));
}
static inline unsigned int blk_rq_count_bios(struct request *rq)
@@ -937,6 +974,7 @@ extern struct request *blk_fetch_request(struct request_queue *q);
*/
extern bool blk_update_request(struct request *rq, int error,
unsigned int nr_bytes);
extern void blk_finish_request(struct request *rq, int error);
extern bool blk_end_request(struct request *rq, int error,
unsigned int nr_bytes);
extern void blk_end_request_all(struct request *rq, int error);
@@ -966,6 +1004,7 @@ extern void blk_queue_make_request(struct request_queue *, make_request_fn *);
extern void blk_queue_bounce_limit(struct request_queue *, u64);
extern void blk_limits_max_hw_sectors(struct queue_limits *, unsigned int);
extern void blk_queue_max_hw_sectors(struct request_queue *, unsigned int);
extern void blk_queue_chunk_sectors(struct request_queue *, unsigned int);
extern void blk_queue_max_segments(struct request_queue *, unsigned short);
extern void blk_queue_max_segment_size(struct request_queue *, unsigned int);
extern void blk_queue_max_discard_sectors(struct request_queue *q,
@@ -1053,7 +1092,6 @@ static inline void blk_post_runtime_resume(struct request_queue *q, int err) {}
* schedule() where blk_schedule_flush_plug() is called.
*/
struct blk_plug {
unsigned long magic; /* detect uninitialized use-cases */
struct list_head list; /* requests */
struct list_head mq_list; /* blk-mq requests */
struct list_head cb_list; /* md requires an unplug callback */
@@ -1102,7 +1140,8 @@ static inline bool blk_needs_flush_plug(struct task_struct *tsk)
/*
* tag stuff
*/
#define blk_rq_tagged(rq) ((rq)->cmd_flags & REQ_QUEUED)
#define blk_rq_tagged(rq) \
((rq)->mq_ctx || ((rq)->cmd_flags & REQ_QUEUED))
extern int blk_queue_start_tag(struct request_queue *, struct request *);
extern struct request *blk_queue_find_tag(struct request_queue *, int);
extern void blk_queue_end_tag(struct request_queue *, struct request *);
@@ -1370,8 +1409,9 @@ static inline void put_dev_sector(Sector p)
}
struct work_struct;
int kblockd_schedule_work(struct request_queue *q, struct work_struct *work);
int kblockd_schedule_delayed_work(struct request_queue *q, struct delayed_work *dwork, unsigned long delay);
int kblockd_schedule_work(struct work_struct *work);
int kblockd_schedule_delayed_work(struct delayed_work *dwork, unsigned long delay);
int kblockd_schedule_delayed_work_on(int cpu, struct delayed_work *dwork, unsigned long delay);
#ifdef CONFIG_BLK_CGROUP
/*
@@ -1570,6 +1610,7 @@ static inline bool blk_integrity_is_initialized(struct gendisk *g)
struct block_device_operations {
int (*open) (struct block_device *, fmode_t);
void (*release) (struct gendisk *, fmode_t);
int (*rw_page)(struct block_device *, sector_t, struct page *, int rw);
int (*ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
int (*compat_ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
int (*direct_access) (struct block_device *, sector_t,
@@ -1588,7 +1629,13 @@ struct block_device_operations {
extern int __blkdev_driver_ioctl(struct block_device *, fmode_t, unsigned int,
unsigned long);
extern int bdev_read_page(struct block_device *, sector_t, struct page *);
extern int bdev_write_page(struct block_device *, sector_t, struct page *,
struct writeback_control *);
#else /* CONFIG_BLOCK */
struct block_device;
/*
* stubs for when the block layer is configured out
*/
@@ -1624,6 +1671,12 @@ static inline bool blk_needs_flush_plug(struct task_struct *tsk)
return false;
}
static inline int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask,
sector_t *error_sector)
{
return 0;
}
#endif /* CONFIG_BLOCK */
#endif

6
include/linux/bootmem.h
View File

@@ -58,9 +58,9 @@ extern void free_bootmem_late(unsigned long physaddr, unsigned long size);
* Flags for reserve_bootmem (also if CONFIG_HAVE_ARCH_BOOTMEM_NODE,
* the architecture-specific code should honor this).
*
* If flags is 0, then the return value is always 0 (success). If
* flags contains BOOTMEM_EXCLUSIVE, then -EBUSY is returned if the
* memory already was reserved.
* If flags is BOOTMEM_DEFAULT, then the return value is always 0 (success).
* If flags contains BOOTMEM_EXCLUSIVE, then -EBUSY is returned if the memory
* already was reserved.
*/
#define BOOTMEM_DEFAULT 0
#define BOOTMEM_EXCLUSIVE (1<<0)

4
include/linux/buffer_head.h
View File

@@ -207,8 +207,6 @@ void block_invalidatepage(struct page *page, unsigned int offset,
unsigned int length);
int block_write_full_page(struct page *page, get_block_t *get_block,
struct writeback_control *wbc);
int block_write_full_page_endio(struct page *page, get_block_t *get_block,
struct writeback_control *wbc, bh_end_io_t *handler);
int block_read_full_page(struct page*, get_block_t*);
int block_is_partially_uptodate(struct page *page, unsigned long from,
unsigned long count);
@@ -278,7 +276,7 @@ static inline void get_bh(struct buffer_head *bh)
static inline void put_bh(struct buffer_head *bh)
{
smp_mb__before_atomic_dec();
smp_mb__before_atomic();
atomic_dec(&bh->b_count);
}

6
include/linux/can/core.h
View File

@@ -10,8 +10,8 @@
*
*/
#ifndef CAN_CORE_H
#define CAN_CORE_H
#ifndef _CAN_CORE_H
#define _CAN_CORE_H
#include <linux/can.h>
#include <linux/skbuff.h>
@@ -58,4 +58,4 @@ extern void can_rx_unregister(struct net_device *dev, canid_t can_id,
extern int can_send(struct sk_buff *skb, int loop);
extern int can_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg);
#endif /* CAN_CORE_H */
#endif /* !_CAN_CORE_H */

6
include/linux/can/dev.h
View File

@@ -10,8 +10,8 @@
*
*/
#ifndef CAN_DEV_H
#define CAN_DEV_H
#ifndef _CAN_DEV_H
#define _CAN_DEV_H
#include <linux/can.h>
#include <linux/can/netlink.h>
@@ -132,4 +132,4 @@ struct sk_buff *alloc_canfd_skb(struct net_device *dev,
struct sk_buff *alloc_can_err_skb(struct net_device *dev,
struct can_frame **cf);
#endif /* CAN_DEV_H */
#endif /* !_CAN_DEV_H */

6
include/linux/can/led.h
View File

@@ -6,8 +6,8 @@
* published by the Free Software Foundation.
*/
#ifndef CAN_LED_H
#define CAN_LED_H
#ifndef _CAN_LED_H
#define _CAN_LED_H
#include <linux/if.h>
#include <linux/leds.h>
@@ -48,4 +48,4 @@ static inline void can_led_notifier_exit(void)
#endif
#endif
#endif /* !_CAN_LED_H */

6
include/linux/can/platform/cc770.h
View File

@@ -1,5 +1,5 @@
#ifndef _CAN_PLATFORM_CC770_H_
#define _CAN_PLATFORM_CC770_H_
#ifndef _CAN_PLATFORM_CC770_H
#define _CAN_PLATFORM_CC770_H
/* CPU Interface Register (0x02) */
#define CPUIF_CEN 0x01 /* Clock Out Enable */
@@ -30,4 +30,4 @@ struct cc770_platform_data {
u8 bcr; /* Bus Configuration Register */
};
#endif /* !_CAN_PLATFORM_CC770_H_ */
#endif /* !_CAN_PLATFORM_CC770_H */

6
include/linux/can/platform/mcp251x.h
View File

@@ -1,5 +1,5 @@
#ifndef __CAN_PLATFORM_MCP251X_H__
#define __CAN_PLATFORM_MCP251X_H__
#ifndef _CAN_PLATFORM_MCP251X_H
#define _CAN_PLATFORM_MCP251X_H
/*
*
@@ -18,4 +18,4 @@ struct mcp251x_platform_data {
unsigned long oscillator_frequency;
};
#endif /* __CAN_PLATFORM_MCP251X_H__ */
#endif /* !_CAN_PLATFORM_MCP251X_H */

17
include/linux/can/platform/rcar_can.h Normal file
View File

@@ -0,0 +1,17 @@
#ifndef _CAN_PLATFORM_RCAR_CAN_H_
#define _CAN_PLATFORM_RCAR_CAN_H_
#include <linux/types.h>
/* Clock Select Register settings */
enum CLKR {
CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */
CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */
CLKR_CLKEXT = 3 /* Externally input clock */
};
struct rcar_can_platform_data {
enum CLKR clock_select; /* Clock source select */
};
#endif /* !_CAN_PLATFORM_RCAR_CAN_H_ */

6
include/linux/can/platform/sja1000.h
View File

@@ -1,5 +1,5 @@
#ifndef _CAN_PLATFORM_SJA1000_H_
#define _CAN_PLATFORM_SJA1000_H_
#ifndef _CAN_PLATFORM_SJA1000_H
#define _CAN_PLATFORM_SJA1000_H
/* clock divider register */
#define CDR_CLKOUT_MASK 0x07
@@ -32,4 +32,4 @@ struct sja1000_platform_data {
u8 cdr; /* clock divider register */
};
#endif /* !_CAN_PLATFORM_SJA1000_H_ */
#endif /* !_CAN_PLATFORM_SJA1000_H */

6
include/linux/can/platform/ti_hecc.h
View File

@@ -1,5 +1,5 @@
#ifndef __CAN_PLATFORM_TI_HECC_H__
#define __CAN_PLATFORM_TI_HECC_H__
#ifndef _CAN_PLATFORM_TI_HECC_H
#define _CAN_PLATFORM_TI_HECC_H
/*
* TI HECC (High End CAN Controller) driver platform header
@@ -41,4 +41,4 @@ struct ti_hecc_platform_data {
u32 version;
void (*transceiver_switch) (int);
};
#endif
#endif /* !_CAN_PLATFORM_TI_HECC_H */

6
include/linux/can/skb.h
View File

@@ -7,8 +7,8 @@
*
*/
#ifndef CAN_SKB_H
#define CAN_SKB_H
#ifndef _CAN_SKB_H
#define _CAN_SKB_H
#include <linux/types.h>
#include <linux/skbuff.h>
@@ -80,4 +80,4 @@ static inline struct sk_buff *can_create_echo_skb(struct sk_buff *skb)
return skb;
}
#endif /* CAN_SKB_H */
#endif /* !_CAN_SKB_H */

2
include/linux/capability.h
View File

@@ -210,7 +210,7 @@ extern bool has_ns_capability_noaudit(struct task_struct *t,
struct user_namespace *ns, int cap);
extern bool capable(int cap);
extern bool ns_capable(struct user_namespace *ns, int cap);
extern bool inode_capable(const struct inode *inode, int cap);
extern bool capable_wrt_inode_uidgid(const struct inode *inode, int cap);
extern bool file_ns_capable(const struct file *file, struct user_namespace *ns, int cap);
/* audit system wants to get cap info from files as well */

2
include/linux/ceph/ceph_fs.h
View File

@@ -625,6 +625,8 @@ int ceph_flags_to_mode(int flags);
CEPH_CAP_LINK_EXCL | \
CEPH_CAP_XATTR_EXCL | \
CEPH_CAP_FILE_EXCL)
#define CEPH_CAP_ANY_FILE_RD (CEPH_CAP_FILE_RD | CEPH_CAP_FILE_CACHE | \
CEPH_CAP_FILE_SHARED)
#define CEPH_CAP_ANY_FILE_WR (CEPH_CAP_FILE_WR | CEPH_CAP_FILE_BUFFER | \
CEPH_CAP_FILE_EXCL)
#define CEPH_CAP_ANY_WR (CEPH_CAP_ANY_EXCL | CEPH_CAP_ANY_FILE_WR)

2
include/linux/ceph/libceph.h
View File

@@ -222,8 +222,6 @@ extern void ceph_copy_to_page_vector(struct page **pages,
extern void ceph_copy_from_page_vector(struct page **pages,
void *data,
loff_t off, size_t len);
extern int ceph_copy_page_vector_to_user(struct page **pages, void __user *data,
loff_t off, size_t len);
extern void ceph_zero_page_vector_range(int off, int len, struct page **pages);

11
include/linux/ceph/mon_client.h
View File

@@ -40,9 +40,9 @@ struct ceph_mon_request {
};
/*
* ceph_mon_generic_request is being used for the statfs and poolop requests
* which are bening done a bit differently because we need to get data back
* to the caller
* ceph_mon_generic_request is being used for the statfs, poolop and
* mon_get_version requests which are being done a bit differently
* because we need to get data back to the caller
*/
struct ceph_mon_generic_request {
struct kref kref;
@@ -104,10 +104,15 @@ extern int ceph_monc_got_mdsmap(struct ceph_mon_client *monc, u32 have);
extern int ceph_monc_got_osdmap(struct ceph_mon_client *monc, u32 have);
extern void ceph_monc_request_next_osdmap(struct ceph_mon_client *monc);
extern int ceph_monc_wait_osdmap(struct ceph_mon_client *monc, u32 epoch,
unsigned long timeout);
extern int ceph_monc_do_statfs(struct ceph_mon_client *monc,
struct ceph_statfs *buf);
extern int ceph_monc_do_get_version(struct ceph_mon_client *monc,
const char *what, u64 *newest);
extern int ceph_monc_open_session(struct ceph_mon_client *monc);
extern int ceph_monc_validate_auth(struct ceph_mon_client *monc);

272
include/linux/cgroup.h
View File

@@ -21,6 +21,7 @@
#include <linux/percpu-refcount.h>
#include <linux/seq_file.h>
#include <linux/kernfs.h>
#include <linux/wait.h>
#ifdef CONFIG_CGROUPS
@@ -47,21 +48,45 @@ enum cgroup_subsys_id {
};
#undef SUBSYS
/* Per-subsystem/per-cgroup state maintained by the system. */
/*
* Per-subsystem/per-cgroup state maintained by the system. This is the
* fundamental structural building block that controllers deal with.
*
* Fields marked with "PI:" are public and immutable and may be accessed
* directly without synchronization.
*/
struct cgroup_subsys_state {
/* the cgroup that this css is attached to */
/* PI: the cgroup that this css is attached to */
struct cgroup *cgroup;
/* the cgroup subsystem that this css is attached to */
/* PI: the cgroup subsystem that this css is attached to */
struct cgroup_subsys *ss;
/* reference count - access via css_[try]get() and css_put() */
struct percpu_ref refcnt;
/* the parent css */
/* PI: the parent css */
struct cgroup_subsys_state *parent;
unsigned long flags;
/* siblings list anchored at the parent's ->children */
struct list_head sibling;
struct list_head children;
/*
* PI: Subsys-unique ID. 0 is unused and root is always 1. The
* matching css can be looked up using css_from_id().
*/
int id;
unsigned int flags;
/*
* Monotonically increasing unique serial number which defines a
* uniform order among all csses. It's guaranteed that all
* ->children lists are in the ascending order of ->serial_nr and
* used to allow interrupting and resuming iterations.
*/
u64 serial_nr;
/* percpu_ref killing and RCU release */
struct rcu_head rcu_head;
@@ -70,8 +95,9 @@ struct cgroup_subsys_state {
/* bits in struct cgroup_subsys_state flags field */
enum {
CSS_ROOT = (1 << 0), /* this CSS is the root of the subsystem */
CSS_NO_REF = (1 << 0), /* no reference counting for this css */
CSS_ONLINE = (1 << 1), /* between ->css_online() and ->css_offline() */
CSS_RELEASED = (1 << 2), /* refcnt reached zero, released */
};
/**
@@ -82,8 +108,7 @@ enum {
*/
static inline void css_get(struct cgroup_subsys_state *css)
{
/* We don't need to reference count the root state */
if (!(css->flags & CSS_ROOT))
if (!(css->flags & CSS_NO_REF))
percpu_ref_get(&css->refcnt);
}
@@ -91,35 +116,51 @@ static inline void css_get(struct cgroup_subsys_state *css)
* css_tryget - try to obtain a reference on the specified css
* @css: target css
*
* Obtain a reference on @css if it's alive. The caller naturally needs to
* ensure that @css is accessible but doesn't have to be holding a
* Obtain a reference on @css unless it already has reached zero and is
* being released. This function doesn't care whether @css is on or
* offline. The caller naturally needs to ensure that @css is accessible
* but doesn't have to be holding a reference on it - IOW, RCU protected
* access is good enough for this function. Returns %true if a reference
* count was successfully obtained; %false otherwise.
*/
static inline bool css_tryget(struct cgroup_subsys_state *css)
{
if (!(css->flags & CSS_NO_REF))
return percpu_ref_tryget(&css->refcnt);
return true;
}
/**
* css_tryget_online - try to obtain a reference on the specified css if online
* @css: target css
*
* Obtain a reference on @css if it's online. The caller naturally needs
* to ensure that @css is accessible but doesn't have to be holding a
* reference on it - IOW, RCU protected access is good enough for this
* function. Returns %true if a reference count was successfully obtained;
* %false otherwise.
*/
static inline bool css_tryget(struct cgroup_subsys_state *css)
static inline bool css_tryget_online(struct cgroup_subsys_state *css)
{
if (css->flags & CSS_ROOT)
return true;
return percpu_ref_tryget(&css->refcnt);
if (!(css->flags & CSS_NO_REF))
return percpu_ref_tryget_live(&css->refcnt);
return true;
}
/**
* css_put - put a css reference
* @css: target css
*
* Put a reference obtained via css_get() and css_tryget().
* Put a reference obtained via css_get() and css_tryget_online().
*/
static inline void css_put(struct cgroup_subsys_state *css)
{
if (!(css->flags & CSS_ROOT))
if (!(css->flags & CSS_NO_REF))
percpu_ref_put(&css->refcnt);
}
/* bits in struct cgroup flags field */
enum {
/* Control Group is dead */
CGRP_DEAD,
/*
* Control Group has previously had a child cgroup or a task,
* but no longer (only if CGRP_NOTIFY_ON_RELEASE is set)
@@ -133,48 +174,37 @@ enum {
* specified at mount time and thus is implemented here.
*/
CGRP_CPUSET_CLONE_CHILDREN,
/* see the comment above CGRP_ROOT_SANE_BEHAVIOR for details */
CGRP_SANE_BEHAVIOR,
};
struct cgroup {
/* self css with NULL ->ss, points back to this cgroup */
struct cgroup_subsys_state self;
unsigned long flags; /* "unsigned long" so bitops work */
/*
* idr allocated in-hierarchy ID.
*
* The ID of the root cgroup is always 0, and a new cgroup
* will be assigned with a smallest available ID.
* ID 0 is not used, the ID of the root cgroup is always 1, and a
* new cgroup will be assigned with a smallest available ID.
*
* Allocating/Removing ID must be protected by cgroup_mutex.
*/
int id;
/* the number of attached css's */
int nr_css;
atomic_t refcnt;
/*
* We link our 'sibling' struct into our parent's 'children'.
* Our children link their 'sibling' into our 'children'.
* If this cgroup contains any tasks, it contributes one to
* populated_cnt. All children with non-zero popuplated_cnt of
* their own contribute one. The count is zero iff there's no task
* in this cgroup or its subtree.
*/
struct list_head sibling; /* my parent's children */
struct list_head children; /* my children */
int populated_cnt;
struct cgroup *parent; /* my parent */
struct kernfs_node *kn; /* cgroup kernfs entry */
struct kernfs_node *populated_kn; /* kn for "cgroup.subtree_populated" */
/*
* Monotonically increasing unique serial number which defines a
* uniform order among all cgroups. It's guaranteed that all
* ->children lists are in the ascending order of ->serial_nr.
* It's used to allow interrupting and resuming iterations.
*/
u64 serial_nr;
/* The bitmask of subsystems attached to this cgroup */
unsigned long subsys_mask;
/* the bitmask of subsystems enabled on the child cgroups */
unsigned int child_subsys_mask;
/* Private pointers for each registered subsystem */
struct cgroup_subsys_state __rcu *subsys[CGROUP_SUBSYS_COUNT];
@@ -187,6 +217,15 @@ struct cgroup {
*/
struct list_head cset_links;
/*
* On the default hierarchy, a css_set for a cgroup with some
* susbsys disabled will point to css's which are associated with
* the closest ancestor which has the subsys enabled. The
* following lists all css_sets which point to this cgroup's css
* for the given subsystem.
*/
struct list_head e_csets[CGROUP_SUBSYS_COUNT];
/*
* Linked list running through all cgroups that can
* potentially be reaped by the release agent. Protected by
@@ -201,12 +240,8 @@ struct cgroup {
struct list_head pidlists;
struct mutex pidlist_mutex;
/* dummy css with NULL ->ss, points back to this cgroup */
struct cgroup_subsys_state dummy_css;
/* For css percpu_ref killing and RCU-protected deletion */
struct rcu_head rcu_head;
struct work_struct destroy_work;
/* used to wait for offlining of csses */
wait_queue_head_t offline_waitq;
};
#define MAX_CGROUP_ROOT_NAMELEN 64
@@ -250,6 +285,12 @@ enum {
*
* - "cgroup.clone_children" is removed.
*
* - "cgroup.subtree_populated" is available. Its value is 0 if
* the cgroup and its descendants contain no task; otherwise, 1.
* The file also generates kernfs notification which can be
* monitored through poll and [di]notify when the value of the
* file changes.
*
* - If mount is requested with sane_behavior but without any
* subsystem, the default unified hierarchy is mounted.
*
@@ -264,6 +305,8 @@ enum {
* the flag is not created.
*
* - blkcg: blk-throttle becomes properly hierarchical.
*
* - debug: disallowed on the default hierarchy.
*/
CGRP_ROOT_SANE_BEHAVIOR = (1 << 0),
@@ -282,6 +325,9 @@ enum {
struct cgroup_root {
struct kernfs_root *kf_root;
/* The bitmask of subsystems attached to this hierarchy */
unsigned int subsys_mask;
/* Unique id for this hierarchy. */
int hierarchy_id;
@@ -295,7 +341,7 @@ struct cgroup_root {
struct list_head root_list;
/* Hierarchy-specific flags */
unsigned long flags;
unsigned int flags;
/* IDs for cgroups in this hierarchy */
struct idr cgroup_idr;
@@ -342,6 +388,9 @@ struct css_set {
*/
struct list_head cgrp_links;
/* the default cgroup associated with this css_set */
struct cgroup *dfl_cgrp;
/*
* Set of subsystem states, one for each subsystem. This array is
* immutable after creation apart from the init_css_set during
@@ -366,6 +415,15 @@ struct css_set {
struct cgroup *mg_src_cgrp;
struct css_set *mg_dst_cset;
/*
* On the default hierarhcy, ->subsys[ssid] may point to a css
* attached to an ancestor instead of the cgroup this css_set is
* associated with. The following node is anchored at
* ->subsys[ssid]->cgroup->e_csets[ssid] and provides a way to
* iterate through all css's attached to a given cgroup.
*/
struct list_head e_cset_node[CGROUP_SUBSYS_COUNT];
/* For RCU-protected deletion */
struct rcu_head rcu_head;
};
@@ -405,8 +463,7 @@ struct cftype {
/*
* The maximum length of string, excluding trailing nul, that can
* be passed to write_string. If < PAGE_SIZE-1, PAGE_SIZE-1 is
* assumed.
* be passed to write. If < PAGE_SIZE-1, PAGE_SIZE-1 is assumed.
*/
size_t max_write_len;
@@ -453,19 +510,13 @@ struct cftype {
s64 val);
/*
* write_string() is passed a nul-terminated kernelspace
* buffer of maximum length determined by max_write_len.
* Returns 0 or -ve error code.
* write() is the generic write callback which maps directly to
* kernfs write operation and overrides all other operations.
* Maximum write size is determined by ->max_write_len. Use
* of_css/cft() to access the associated css and cft.
*/
int (*write_string)(struct cgroup_subsys_state *css, struct cftype *cft,
char *buffer);
/*
* trigger() callback can be used to get some kick from the
* userspace, when the actual string written is not important
* at all. The private field can be used to determine the
* kick type for multiplexing.
*/
int (*trigger)(struct cgroup_subsys_state *css, unsigned int event);
ssize_t (*write)(struct kernfs_open_file *of,
char *buf, size_t nbytes, loff_t off);
#ifdef CONFIG_DEBUG_LOCK_ALLOC
struct lock_class_key lockdep_key;
@@ -504,14 +555,24 @@ static inline ino_t cgroup_ino(struct cgroup *cgrp)
return 0;
}
static inline struct cftype *seq_cft(struct seq_file *seq)
/* cft/css accessors for cftype->write() operation */
static inline struct cftype *of_cft(struct kernfs_open_file *of)
{
struct kernfs_open_file *of = seq->private;
return of->kn->priv;
}
struct cgroup_subsys_state *seq_css(struct seq_file *seq);
struct cgroup_subsys_state *of_css(struct kernfs_open_file *of);
/* cft/css accessors for cftype->seq_*() operations */
static inline struct cftype *seq_cft(struct seq_file *seq)
{
return of_cft(seq->private);
}
static inline struct cgroup_subsys_state *seq_css(struct seq_file *seq)
{
return of_css(seq->private);
}
/*
* Name / path handling functions. All are thin wrappers around the kernfs
@@ -612,6 +673,9 @@ struct cgroup_subsys {
/* link to parent, protected by cgroup_lock() */
struct cgroup_root *root;
/* idr for css->id */
struct idr css_idr;
/*
* List of cftypes. Each entry is the first entry of an array
* terminated by zero length name.
@@ -626,19 +690,6 @@ struct cgroup_subsys {
#include <linux/cgroup_subsys.h>
#undef SUBSYS
/**
* css_parent - find the parent css
* @css: the target cgroup_subsys_state
*
* Return the parent css of @css. This function is guaranteed to return
* non-NULL parent as long as @css isn't the root.
*/
static inline
struct cgroup_subsys_state *css_parent(struct cgroup_subsys_state *css)
{
return css->parent;
}
/**
* task_css_set_check - obtain a task's css_set with extra access conditions
* @task: the task to obtain css_set for
@@ -731,14 +782,14 @@ struct cgroup_subsys_state *css_from_id(int id, struct cgroup_subsys *ss);
* @pos: the css * to use as the loop cursor
* @parent: css whose children to walk
*
* Walk @parent's children. Must be called under rcu_read_lock(). A child
* css which hasn't finished ->css_online() or already has finished
* ->css_offline() may show up during traversal and it's each subsystem's
* responsibility to verify that each @pos is alive.
* Walk @parent's children. Must be called under rcu_read_lock().
*
* If a subsystem synchronizes against the parent in its ->css_online() and
* before starting iterating, a css which finished ->css_online() is
* guaranteed to be visible in the future iterations.
* If a subsystem synchronizes ->css_online() and the start of iteration, a
* css which finished ->css_online() is guaranteed to be visible in the
* future iterations and will stay visible until the last reference is put.
* A css which hasn't finished ->css_online() or already finished
* ->css_offline() may show up during traversal. It's each subsystem's
* responsibility to synchronize against on/offlining.
*
* It is allowed to temporarily drop RCU read lock during iteration. The
* caller is responsible for ensuring that @pos remains accessible until
@@ -761,17 +812,16 @@ css_rightmost_descendant(struct cgroup_subsys_state *pos);
* @root: css whose descendants to walk
*
* Walk @root's descendants. @root is included in the iteration and the
* first node to be visited. Must be called under rcu_read_lock(). A
* descendant css which hasn't finished ->css_online() or already has
* finished ->css_offline() may show up during traversal and it's each
* subsystem's responsibility to verify that each @pos is alive.
* first node to be visited. Must be called under rcu_read_lock().
*
* If a subsystem synchronizes against the parent in its ->css_online() and
* before starting iterating, and synchronizes against @pos on each
* iteration, any descendant css which finished ->css_online() is
* guaranteed to be visible in the future iterations.
* If a subsystem synchronizes ->css_online() and the start of iteration, a
* css which finished ->css_online() is guaranteed to be visible in the
* future iterations and will stay visible until the last reference is put.
* A css which hasn't finished ->css_online() or already finished
* ->css_offline() may show up during traversal. It's each subsystem's
* responsibility to synchronize against on/offlining.
*
* In other words, the following guarantees that a descendant can't escape
* For example, the following guarantees that a descendant can't escape
* state updates of its ancestors.
*
* my_online(@css)
@@ -827,18 +877,34 @@ css_next_descendant_post(struct cgroup_subsys_state *pos,
*
* Similar to css_for_each_descendant_pre() but performs post-order
* traversal instead. @root is included in the iteration and the last
* node to be visited. Note that the walk visibility guarantee described
* in pre-order walk doesn't apply the same to post-order walks.
* node to be visited.
*
* If a subsystem synchronizes ->css_online() and the start of iteration, a
* css which finished ->css_online() is guaranteed to be visible in the
* future iterations and will stay visible until the last reference is put.
* A css which hasn't finished ->css_online() or already finished
* ->css_offline() may show up during traversal. It's each subsystem's
* responsibility to synchronize against on/offlining.
*
* Note that the walk visibility guarantee example described in pre-order
* walk doesn't apply the same to post-order walks.
*/
#define css_for_each_descendant_post(pos, css) \
for ((pos) = css_next_descendant_post(NULL, (css)); (pos); \
(pos) = css_next_descendant_post((pos), (css)))
bool css_has_online_children(struct cgroup_subsys_state *css);
/* A css_task_iter should be treated as an opaque object */
struct css_task_iter {
struct cgroup_subsys_state *origin_css;
struct list_head *cset_link;
struct list_head *task;
struct cgroup_subsys *ss;
struct list_head *cset_pos;
struct list_head *cset_head;
struct list_head *task_pos;
struct list_head *tasks_head;
struct list_head *mg_tasks_head;
};
void css_task_iter_start(struct cgroup_subsys_state *css,
@@ -849,8 +915,8 @@ void css_task_iter_end(struct css_task_iter *it);
int cgroup_attach_task_all(struct task_struct *from, struct task_struct *);
int cgroup_transfer_tasks(struct cgroup *to, struct cgroup *from);
struct cgroup_subsys_state *css_tryget_from_dir(struct dentry *dentry,
struct cgroup_subsys *ss);
struct cgroup_subsys_state *css_tryget_online_from_dir(struct dentry *dentry,
struct cgroup_subsys *ss);
#else /* !CONFIG_CGROUPS */

11
include/linux/cgroup_subsys.h
View File

@@ -7,10 +7,6 @@
SUBSYS(cpuset)
#endif
#if IS_ENABLED(CONFIG_CGROUP_DEBUG)
SUBSYS(debug)
#endif
#if IS_ENABLED(CONFIG_CGROUP_SCHED)
SUBSYS(cpu)
#endif
@@ -50,6 +46,13 @@ SUBSYS(net_prio)
#if IS_ENABLED(CONFIG_CGROUP_HUGETLB)
SUBSYS(hugetlb)
#endif
/*
* The following subsystems are not supported on the default hierarchy.
*/
#if IS_ENABLED(CONFIG_CGROUP_DEBUG)
SUBSYS(debug)
#endif
/*
* DO NOT ADD ANY SUBSYSTEM WITHOUT EXPLICIT ACKS FROM CGROUP MAINTAINERS.
*/

132
include/linux/clk-provider.h
View File

@@ -40,14 +40,14 @@ struct dentry;
* through the clk_* api.
*
* @prepare: Prepare the clock for enabling. This must not return until
* the clock is fully prepared, and it's safe to call clk_enable.
* This callback is intended to allow clock implementations to
* do any initialisation that may sleep. Called with
* prepare_lock held.
* the clock is fully prepared, and it's safe to call clk_enable.
* This callback is intended to allow clock implementations to
* do any initialisation that may sleep. Called with
* prepare_lock held.
*
* @unprepare: Release the clock from its prepared state. This will typically
* undo any work done in the @prepare callback. Called with
* prepare_lock held.
* undo any work done in the @prepare callback. Called with
* prepare_lock held.
*
* @is_prepared: Queries the hardware to determine if the clock is prepared.
* This function is allowed to sleep. Optional, if this op is not
@@ -58,16 +58,16 @@ struct dentry;
* Called with prepare mutex held. This function may sleep.
*
* @enable: Enable the clock atomically. This must not return until the
* clock is generating a valid clock signal, usable by consumer
* devices. Called with enable_lock held. This function must not
* sleep.
* clock is generating a valid clock signal, usable by consumer
* devices. Called with enable_lock held. This function must not
* sleep.
*
* @disable: Disable the clock atomically. Called with enable_lock held.
* This function must not sleep.
* This function must not sleep.
*
* @is_enabled: Queries the hardware to determine if the clock is enabled.
* This function must not sleep. Optional, if this op is not
* set then the enable count will be used.
* This function must not sleep. Optional, if this op is not
* set then the enable count will be used.
*
* @disable_unused: Disable the clock atomically. Only called from
* clk_disable_unused for gate clocks with special needs.
@@ -75,34 +75,35 @@ struct dentry;
* sleep.
*
* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
* parent rate is an input parameter. It is up to the caller to
* ensure that the prepare_mutex is held across this call.
* Returns the calculated rate. Optional, but recommended - if
* this op is not set then clock rate will be initialized to 0.
* parent rate is an input parameter. It is up to the caller to
* ensure that the prepare_mutex is held across this call.
* Returns the calculated rate. Optional, but recommended - if
* this op is not set then clock rate will be initialized to 0.
*
* @round_rate: Given a target rate as input, returns the closest rate actually
* supported by the clock.
* supported by the clock. The parent rate is an input/output
* parameter.
*
* @determine_rate: Given a target rate as input, returns the closest rate
* actually supported by the clock, and optionally the parent clock
* that should be used to provide the clock rate.
*
* @get_parent: Queries the hardware to determine the parent of a clock. The
* return value is a u8 which specifies the index corresponding to
* the parent clock. This index can be applied to either the
* .parent_names or .parents arrays. In short, this function
* translates the parent value read from hardware into an array
* index. Currently only called when the clock is initialized by
* __clk_init. This callback is mandatory for clocks with
* multiple parents. It is optional (and unnecessary) for clocks
* with 0 or 1 parents.
*
* @set_parent: Change the input source of this clock; for clocks with multiple
* possible parents specify a new parent by passing in the index
* as a u8 corresponding to the parent in either the .parent_names
* or .parents arrays. This function in affect translates an
* array index into the value programmed into the hardware.
* Returns 0 on success, -EERROR otherwise.
* possible parents specify a new parent by passing in the index
* as a u8 corresponding to the parent in either the .parent_names
* or .parents arrays. This function in affect translates an
* array index into the value programmed into the hardware.
* Returns 0 on success, -EERROR otherwise.
*
* @get_parent: Queries the hardware to determine the parent of a clock. The
* return value is a u8 which specifies the index corresponding to
* the parent clock. This index can be applied to either the
* .parent_names or .parents arrays. In short, this function
* translates the parent value read from hardware into an array
* index. Currently only called when the clock is initialized by
* __clk_init. This callback is mandatory for clocks with
* multiple parents. It is optional (and unnecessary) for clocks
* with 0 or 1 parents.
*
* @set_rate: Change the rate of this clock. The requested rate is specified
* by the second argument, which should typically be the return
@@ -110,13 +111,6 @@ struct dentry;
* which is likely helpful for most .set_rate implementation.
* Returns 0 on success, -EERROR otherwise.
*
* @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
* is expressed in ppb (parts per billion). The parent accuracy is
* an input parameter.
* Returns the calculated accuracy. Optional - if this op is not
* set then clock accuracy will be initialized to parent accuracy
* or 0 (perfect clock) if clock has no parent.
*
* @set_rate_and_parent: Change the rate and the parent of this clock. The
* requested rate is specified by the second argument, which
* should typically be the return of .round_rate call. The
@@ -128,6 +122,18 @@ struct dentry;
* separately via calls to .set_parent and .set_rate.
* Returns 0 on success, -EERROR otherwise.
*
* @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
* is expressed in ppb (parts per billion). The parent accuracy is
* an input parameter.
* Returns the calculated accuracy. Optional - if this op is not
* set then clock accuracy will be initialized to parent accuracy
* or 0 (perfect clock) if clock has no parent.
*
* @init: Perform platform-specific initialization magic.
* This is not not used by any of the basic clock types.
* Please consider other ways of solving initialization problems
* before using this callback, as its use is discouraged.
*
* @debug_init: Set up type-specific debugfs entries for this clock. This
* is called once, after the debugfs directory entry for this
* clock has been created. The dentry pointer representing that
@@ -157,15 +163,15 @@ struct clk_ops {
void (*disable_unused)(struct clk_hw *hw);
unsigned long (*recalc_rate)(struct clk_hw *hw,
unsigned long parent_rate);
long (*round_rate)(struct clk_hw *hw, unsigned long,
unsigned long *);
long (*round_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate);
long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate,
struct clk **best_parent_clk);
int (*set_parent)(struct clk_hw *hw, u8 index);
u8 (*get_parent)(struct clk_hw *hw);
int (*set_rate)(struct clk_hw *hw, unsigned long,
unsigned long);
int (*set_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
int (*set_rate_and_parent)(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate, u8 index);
@@ -254,12 +260,12 @@ void of_fixed_clk_setup(struct device_node *np);
*
* Flags:
* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
* enable the clock. Setting this flag does the opposite: setting the bit
* disable the clock and clearing it enables the clock
* enable the clock. Setting this flag does the opposite: setting the bit
* disable the clock and clearing it enables the clock
* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
* of this register, and mask of gate bits are in higher 16-bit of this
* register. While setting the gate bits, higher 16-bit should also be
* updated to indicate changing gate bits.
* of this register, and mask of gate bits are in higher 16-bit of this
* register. While setting the gate bits, higher 16-bit should also be
* updated to indicate changing gate bits.
*/
struct clk_gate {
struct clk_hw hw;
@@ -298,20 +304,24 @@ struct clk_div_table {
*
* Flags:
* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
* the raw value read from the register, with the value of zero considered
* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
* the raw value read from the register, with the value of zero considered
* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
* the hardware register
* the hardware register
* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
* CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
* Some hardware implementations gracefully handle this case and allow a
* zero divisor by not modifying their input clock
* (divide by one / bypass).
* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
* of this register, and mask of divider bits are in higher 16-bit of this
* register. While setting the divider bits, higher 16-bit should also be
* updated to indicate changing divider bits.
* of this register, and mask of divider bits are in higher 16-bit of this
* register. While setting the divider bits, higher 16-bit should also be
* updated to indicate changing divider bits.
* CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
* to the closest integer instead of the up one.
* CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
* not be changed by the clock framework.
*/
struct clk_divider {
struct clk_hw hw;
@@ -327,8 +337,11 @@ struct clk_divider {
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
extern const struct clk_ops clk_divider_ops;
extern const struct clk_ops clk_divider_ro_ops;
struct clk *clk_register_divider(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
@@ -356,9 +369,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
* CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
* CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
* register, and mask of mux bits are in higher 16-bit of this register.
* While setting the mux bits, higher 16-bit should also be updated to
* indicate changing mux bits.
* register, and mask of mux bits are in higher 16-bit of this register.
* While setting the mux bits, higher 16-bit should also be updated to
* indicate changing mux bits.
*/
struct clk_mux {
struct clk_hw hw;
@@ -529,10 +542,7 @@ struct clk_onecell_data {
extern struct of_device_id __clk_of_table;
#define CLK_OF_DECLARE(name, compat, fn) \
static const struct of_device_id __clk_of_table_##name \
__used __section(__clk_of_table) \
= { .compatible = compat, .data = fn };
#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
#ifdef CONFIG_OF
int of_clk_add_provider(struct device_node *np,

1
include/linux/clk/at91_pmc.h
View File

@@ -155,6 +155,7 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */

3
include/linux/clk/shmobile.h
View File

@@ -1,7 +1,9 @@
/*
* Copyright 2013 Ideas On Board SPRL
* Copyright 2013, 2014 Horms Solutions Ltd.
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Contact: Simon Horman <horms@verge.net.au>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
#include <linux/types.h>
void r8a7779_clocks_init(u32 mode);
void rcar_gen2_clocks_init(u32 mode);
#endif

22
include/linux/clk/sunxi.h Normal file
View File

@@ -0,0 +1,22 @@
/*
* Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_CLK_SUNXI_H_
#define __LINUX_CLK_SUNXI_H_
#include <linux/clk.h>
void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
#endif

35
include/linux/clk/ti.h
View File

@@ -41,6 +41,8 @@
* @idlest_reg: register containing the DPLL idle status bitfield
* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
* @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
* @dcc_rate: rate atleast which DCC @dcc_mask must be set
* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
@@ -86,6 +88,8 @@ struct dpll_data {
u32 idlest_mask;
u32 dco_mask;
u32 sddiv_mask;
u32 dcc_mask;
unsigned long dcc_rate;
u32 lpmode_mask;
u32 m4xen_mask;
u8 auto_recal_bit;
@@ -94,7 +98,26 @@ struct dpll_data {
u8 flags;
};
struct clk_hw_omap_ops;
struct clk_hw_omap;
/**
* struct clk_hw_omap_ops - OMAP clk ops
* @find_idlest: find idlest register information for a clock
* @find_companion: find companion clock register information for a clock,
* basically converts CM_ICLKEN* <-> CM_FCLKEN*
* @allow_idle: enables autoidle hardware functionality for a clock
* @deny_idle: prevent autoidle hardware functionality for a clock
*/
struct clk_hw_omap_ops {
void (*find_idlest)(struct clk_hw_omap *oclk,
void __iomem **idlest_reg,
u8 *idlest_bit, u8 *idlest_val);
void (*find_companion)(struct clk_hw_omap *oclk,
void __iomem **other_reg,
u8 *other_bit);
void (*allow_idle)(struct clk_hw_omap *oclk);
void (*deny_idle)(struct clk_hw_omap *oclk);
};
/**
* struct clk_hw_omap - OMAP struct clk
@@ -259,6 +282,12 @@ int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap3_clk_lock_dpll5(void);
unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
unsigned long parent_rate);
int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
void omap2xxx_clkt_vps_init(void);
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
@@ -278,6 +307,8 @@ int omap5xxx_dt_clk_init(void);
int dra7xx_dt_clk_init(void);
int am33xx_dt_clk_init(void);
int am43xx_dt_clk_init(void);
int omap2420_dt_clk_init(void);
int omap2430_dt_clk_init(void);
#ifdef CONFIG_OF
void of_ti_clk_allow_autoidle_all(void);
@@ -287,6 +318,8 @@ static inline void of_ti_clk_allow_autoidle_all(void) { }
static inline void of_ti_clk_deny_autoidle_all(void) { }
#endif
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;

16
include/linux/clocksource.h
View File

@@ -339,23 +339,13 @@ extern int clocksource_mmio_init(void __iomem *, const char *,
extern int clocksource_i8253_init(void);
struct device_node;
typedef void(*clocksource_of_init_fn)(struct device_node *);
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
OF_DECLARE_1(clksrc, name, compat, fn)
#ifdef CONFIG_CLKSRC_OF
extern void clocksource_of_init(void);
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
static const struct of_device_id __clksrc_of_table_##name \
__used __section(__clksrc_of_table) \
= { .compatible = compat, \
.data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn }
#else
static inline void clocksource_of_init(void) {}
#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \
static const struct of_device_id __clksrc_of_table_##name \
__attribute__((unused)) \
= { .compatible = compat, \
.data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn }
#endif
#endif /* _LINUX_CLOCKSOURCE_H */

4
include/linux/compaction.h
View File

@@ -22,7 +22,7 @@ extern int sysctl_extfrag_handler(struct ctl_table *table, int write,
extern int fragmentation_index(struct zone *zone, unsigned int order);
extern unsigned long try_to_compact_pages(struct zonelist *zonelist,
int order, gfp_t gfp_mask, nodemask_t *mask,
bool sync, bool *contended);
enum migrate_mode mode, bool *contended);
extern void compact_pgdat(pg_data_t *pgdat, int order);
extern void reset_isolation_suitable(pg_data_t *pgdat);
extern unsigned long compaction_suitable(struct zone *zone, int order);
@@ -91,7 +91,7 @@ static inline bool compaction_restarting(struct zone *zone, int order)
#else
static inline unsigned long try_to_compact_pages(struct zonelist *zonelist,
int order, gfp_t gfp_mask, nodemask_t *nodemask,
bool sync, bool *contended)
enum migrate_mode mode, bool *contended)
{
return COMPACT_CONTINUE;
}

3
include/linux/compiler-intel.h
View File

@@ -13,12 +13,9 @@
/* Intel ECC compiler doesn't support gcc specific asm stmts.
* It uses intrinsics to do the equivalent things.
*/
#undef barrier
#undef RELOC_HIDE
#undef OPTIMIZER_HIDE_VAR
#define barrier() __memory_barrier()
#define RELOC_HIDE(ptr, off) \
({ unsigned long __ptr; \
__ptr = (unsigned long) (ptr); \

15
include/linux/compiler.h
View File

@@ -323,9 +323,18 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
#endif
#ifndef __compiletime_error
# define __compiletime_error(message)
# define __compiletime_error_fallback(condition) \
/*
* Sparse complains of variable sized arrays due to the temporary variable in
* __compiletime_assert. Unfortunately we can't just expand it out to make
* sparse see a constant array size without breaking compiletime_assert on old
* versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether.
*/
# ifndef __CHECKER__
# define __compiletime_error_fallback(condition) \
do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
#else
# endif
#endif
#ifndef __compiletime_error_fallback
# define __compiletime_error_fallback(condition) do { } while (0)
#endif
@@ -374,7 +383,9 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */
#ifdef CONFIG_KPROBES
# define __kprobes __attribute__((__section__(".kprobes.text")))
# define nokprobe_inline __always_inline
#else
# define __kprobes
# define nokprobe_inline inline
#endif
#endif /* __LINUX_COMPILER_H */

1
include/linux/connector.h
View File

@@ -71,6 +71,7 @@ struct cn_dev {
int cn_add_callback(struct cb_id *id, const char *name,
void (*callback)(struct cn_msg *, struct netlink_skb_parms *));
void cn_del_callback(struct cb_id *);
int cn_netlink_send_mult(struct cn_msg *msg, u16 len, u32 portid, u32 group, gfp_t gfp_mask);
int cn_netlink_send(struct cn_msg *msg, u32 portid, u32 group, gfp_t gfp_mask);
int cn_queue_add_callback(struct cn_queue_dev *dev, const char *name,

5
include/linux/console_struct.h
View File

@@ -17,6 +17,7 @@
#include <linux/workqueue.h>
struct vt_struct;
struct uni_pagedir;
#define NPAR 16
@@ -104,8 +105,8 @@ struct vc_data {
unsigned int vc_bell_pitch; /* Console bell pitch */
unsigned int vc_bell_duration; /* Console bell duration */
struct vc_data **vc_display_fg; /* [!] Ptr to var holding fg console for this display */
unsigned long vc_uni_pagedir;
unsigned long *vc_uni_pagedir_loc; /* [!] Location of uni_pagedir variable for this console */
struct uni_pagedir *vc_uni_pagedir;
struct uni_pagedir **vc_uni_pagedir_loc; /* [!] Location of uni_pagedir variable for this console */
bool vc_panic_force_write; /* when oops/panic this VC can accept forced output/blanking */
/* additional information is in vt_kern.h */
};

1
include/linux/cpu.h
View File

@@ -256,7 +256,6 @@ enum cpuhp_state {
};
void cpu_startup_entry(enum cpuhp_state state);
void cpu_idle(void);
void cpu_idle_poll_ctrl(bool enable);

75
include/linux/cpufreq.h
View File

@@ -75,6 +75,7 @@ struct cpufreq_policy {
unsigned int max; /* in kHz */
unsigned int cur; /* in kHz, only needed if cpufreq
* governors are used */
unsigned int restore_freq; /* = policy->cur before transition */
unsigned int suspend_freq; /* freq to set during suspend */
unsigned int policy; /* see above */
@@ -110,6 +111,7 @@ struct cpufreq_policy {
bool transition_ongoing; /* Tracks transition status */
spinlock_t transition_lock;
wait_queue_head_t transition_wait;
struct task_struct *transition_task; /* Task which is doing the transition */
};
/* Only for ACPI */
@@ -220,11 +222,35 @@ struct cpufreq_driver {
/* define one out of two */
int (*setpolicy) (struct cpufreq_policy *policy);
/*
* On failure, should always restore frequency to policy->restore_freq
* (i.e. old freq).
*/
int (*target) (struct cpufreq_policy *policy, /* Deprecated */
unsigned int target_freq,
unsigned int relation);
int (*target_index) (struct cpufreq_policy *policy,
unsigned int index);
/*
* Only for drivers with target_index() and CPUFREQ_ASYNC_NOTIFICATION
* unset.
*
* get_intermediate should return a stable intermediate frequency
* platform wants to switch to and target_intermediate() should set CPU
* to to that frequency, before jumping to the frequency corresponding
* to 'index'. Core will take care of sending notifications and driver
* doesn't have to handle them in target_intermediate() or
* target_index().
*
* Drivers can return '0' from get_intermediate() in case they don't
* wish to switch to intermediate frequency for some target frequency.
* In that case core will directly call ->target_index().
*/
unsigned int (*get_intermediate)(struct cpufreq_policy *policy,
unsigned int index);
int (*target_intermediate)(struct cpufreq_policy *policy,
unsigned int index);
/* should be defined, if possible */
unsigned int (*get) (unsigned int cpu);
@@ -468,6 +494,55 @@ struct cpufreq_frequency_table {
* order */
};
#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_PM_OPP)
int dev_pm_opp_init_cpufreq_table(struct device *dev,
struct cpufreq_frequency_table **table);
void dev_pm_opp_free_cpufreq_table(struct device *dev,
struct cpufreq_frequency_table **table);
#else
static inline int dev_pm_opp_init_cpufreq_table(struct device *dev,
struct cpufreq_frequency_table
**table)
{
return -EINVAL;
}
static inline void dev_pm_opp_free_cpufreq_table(struct device *dev,
struct cpufreq_frequency_table
**table)
{
}
#endif
static inline bool cpufreq_next_valid(struct cpufreq_frequency_table **pos)
{
while ((*pos)->frequency != CPUFREQ_TABLE_END)
if ((*pos)->frequency != CPUFREQ_ENTRY_INVALID)
return true;
else
(*pos)++;
return false;
}
/*
* cpufreq_for_each_entry - iterate over a cpufreq_frequency_table
* @pos: the cpufreq_frequency_table * to use as a loop cursor.
* @table: the cpufreq_frequency_table * to iterate over.
*/
#define cpufreq_for_each_entry(pos, table) \
for (pos = table; pos->frequency != CPUFREQ_TABLE_END; pos++)
/*
* cpufreq_for_each_valid_entry - iterate over a cpufreq_frequency_table
* excluding CPUFREQ_ENTRY_INVALID frequencies.
* @pos: the cpufreq_frequency_table * to use as a loop cursor.
* @table: the cpufreq_frequency_table * to iterate over.
*/
#define cpufreq_for_each_valid_entry(pos, table) \
for (pos = table; cpufreq_next_valid(&pos); pos++)
int cpufreq_frequency_table_cpuinfo(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table);

1
include/linux/cpuidle.h
View File

@@ -84,6 +84,7 @@ struct cpuidle_device {
};
DECLARE_PER_CPU(struct cpuidle_device *, cpuidle_devices);
DECLARE_PER_CPU(struct cpuidle_device, cpuidle_dev);
/**
* cpuidle_get_last_residency - retrieves the last state's residency time

10
include/linux/cpumask.h
View File

@@ -142,6 +142,13 @@ static inline unsigned int cpumask_any_but(const struct cpumask *mask,
return 1;
}
static inline int cpumask_set_cpu_local_first(int i, int numa_node, cpumask_t *dstp)
{
set_bit(0, cpumask_bits(dstp));
return 0;
}
#define for_each_cpu(cpu, mask) \
for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)
#define for_each_cpu_not(cpu, mask) \
@@ -192,6 +199,7 @@ static inline unsigned int cpumask_next_zero(int n, const struct cpumask *srcp)
int cpumask_next_and(int n, const struct cpumask *, const struct cpumask *);
int cpumask_any_but(const struct cpumask *mask, unsigned int cpu);
int cpumask_set_cpu_local_first(int i, int numa_node, cpumask_t *dstp);
/**
* for_each_cpu - iterate over every cpu in a mask
@@ -600,7 +608,7 @@ static inline int cpulist_scnprintf(char *buf, int len,
static inline int cpumask_parse(const char *buf, struct cpumask *dstp)
{
char *nl = strchr(buf, '\n');
int len = nl ? nl - buf : strlen(buf);
unsigned int len = nl ? (unsigned int)(nl - buf) : strlen(buf);
return bitmap_parse(buf, len, cpumask_bits(dstp), nr_cpumask_bits);
}

29
include/linux/cpuset.h
View File

@@ -12,10 +12,31 @@
#include <linux/cpumask.h>
#include <linux/nodemask.h>
#include <linux/mm.h>
#include <linux/jump_label.h>
#ifdef CONFIG_CPUSETS
extern int number_of_cpusets; /* How many cpusets are defined in system? */
extern struct static_key cpusets_enabled_key;
static inline bool cpusets_enabled(void)
{
return static_key_false(&cpusets_enabled_key);
}
static inline int nr_cpusets(void)
{
/* jump label reference count + the top-level cpuset */
return static_key_count(&cpusets_enabled_key) + 1;
}
static inline void cpuset_inc(void)
{
static_key_slow_inc(&cpusets_enabled_key);
}
static inline void cpuset_dec(void)
{
static_key_slow_dec(&cpusets_enabled_key);
}
extern int cpuset_init(void);
extern void cpuset_init_smp(void);
@@ -32,13 +53,13 @@ extern int __cpuset_node_allowed_hardwall(int node, gfp_t gfp_mask);
static inline int cpuset_node_allowed_softwall(int node, gfp_t gfp_mask)
{
return number_of_cpusets <= 1 ||
return nr_cpusets() <= 1 ||
__cpuset_node_allowed_softwall(node, gfp_mask);
}
static inline int cpuset_node_allowed_hardwall(int node, gfp_t gfp_mask)
{
return number_of_cpusets <= 1 ||
return nr_cpusets() <= 1 ||
__cpuset_node_allowed_hardwall(node, gfp_mask);
}
@@ -124,6 +145,8 @@ static inline void set_mems_allowed(nodemask_t nodemask)
#else /* !CONFIG_CPUSETS */
static inline bool cpusets_enabled(void) { return false; }
static inline int cpuset_init(void) { return 0; }
static inline void cpuset_init_smp(void) {}

8
include/linux/crc7.h
View File

@@ -2,13 +2,13 @@
#define _LINUX_CRC7_H
#include <linux/types.h>
extern const u8 crc7_syndrome_table[256];
extern const u8 crc7_be_syndrome_table[256];
static inline u8 crc7_byte(u8 crc, u8 data)
static inline u8 crc7_be_byte(u8 crc, u8 data)
{
return crc7_syndrome_table[(crc << 1) ^ data];
return crc7_be_syndrome_table[crc ^ data];
}
extern u8 crc7(u8 crc, const u8 *buffer, size_t len);
extern u8 crc7_be(u8 crc, const u8 *buffer, size_t len);
#endif

10
include/linux/dell-led.h Normal file
View File

@@ -0,0 +1,10 @@
#ifndef __DELL_LED_H__
#define __DELL_LED_H__
enum {
DELL_LED_MICMUTE,
};
int dell_app_wmi_led_set(int whichled, int on);
#endif

35
include/linux/devfreq.h
View File

@@ -181,6 +181,12 @@ extern struct devfreq *devfreq_add_device(struct device *dev,
const char *governor_name,
void *data);
extern int devfreq_remove_device(struct devfreq *devfreq);
extern struct devfreq *devm_devfreq_add_device(struct device *dev,
struct devfreq_dev_profile *profile,
const char *governor_name,
void *data);
extern void devm_devfreq_remove_device(struct device *dev,
struct devfreq *devfreq);
/* Supposed to be called by PM_SLEEP/PM_RUNTIME callbacks */
extern int devfreq_suspend_device(struct devfreq *devfreq);
@@ -193,6 +199,10 @@ extern int devfreq_register_opp_notifier(struct device *dev,
struct devfreq *devfreq);
extern int devfreq_unregister_opp_notifier(struct device *dev,
struct devfreq *devfreq);
extern int devm_devfreq_register_opp_notifier(struct device *dev,
struct devfreq *devfreq);
extern void devm_devfreq_unregister_opp_notifier(struct device *dev,
struct devfreq *devfreq);
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
/**
@@ -220,7 +230,7 @@ static inline struct devfreq *devfreq_add_device(struct device *dev,
const char *governor_name,
void *data)
{
return NULL;
return ERR_PTR(-ENOSYS);
}
static inline int devfreq_remove_device(struct devfreq *devfreq)
@@ -228,6 +238,19 @@ static inline int devfreq_remove_device(struct devfreq *devfreq)
return 0;
}
static inline struct devfreq *devm_devfreq_add_device(struct device *dev,
struct devfreq_dev_profile *profile,
const char *governor_name,
void *data)
{
return ERR_PTR(-ENOSYS);
}
static inline void devm_devfreq_remove_device(struct device *dev,
struct devfreq *devfreq)
{
}
static inline int devfreq_suspend_device(struct devfreq *devfreq)
{
return 0;
@@ -256,6 +279,16 @@ static inline int devfreq_unregister_opp_notifier(struct device *dev,
return -EINVAL;
}
static inline int devm_devfreq_register_opp_notifier(struct device *dev,
struct devfreq *devfreq)
{
return -EINVAL;
}
static inline void devm_devfreq_unregister_opp_notifier(struct device *dev,
struct devfreq *devfreq)
{
}
#endif /* CONFIG_PM_DEVFREQ */
#endif /* __LINUX_DEVFREQ_H__ */

10
include/linux/device-mapper.h
View File

@@ -115,12 +115,6 @@ typedef int (*dm_busy_fn) (struct dm_target *ti);
void dm_error(const char *message);
/*
* Combine device limits.
*/
int dm_set_device_limits(struct dm_target *ti, struct dm_dev *dev,
sector_t start, sector_t len, void *data);
struct dm_dev {
struct block_device *bdev;
fmode_t mode;
@@ -132,7 +126,7 @@ struct dm_dev {
* are opened/closed correctly.
*/
int dm_get_device(struct dm_target *ti, const char *path, fmode_t mode,
struct dm_dev **result);
struct dm_dev **result);
void dm_put_device(struct dm_target *ti, struct dm_dev *d);
/*
@@ -291,6 +285,7 @@ struct dm_target_io {
struct dm_io *io;
struct dm_target *ti;
unsigned target_bio_nr;
unsigned *len_ptr;
struct bio clone;
};
@@ -401,6 +396,7 @@ int dm_copy_name_and_uuid(struct mapped_device *md, char *name, char *uuid);
struct gendisk *dm_disk(struct mapped_device *md);
int dm_suspended(struct dm_target *ti);
int dm_noflush_suspending(struct dm_target *ti);
void dm_accept_partial_bio(struct bio *bio, unsigned n_sectors);
union map_info *dm_get_rq_mapinfo(struct request *rq);
struct queue_limits *dm_get_queue_limits(struct mapped_device *md);

23
include/linux/device.h
View File

@@ -623,6 +623,12 @@ static inline void *devm_kcalloc(struct device *dev,
}
extern void devm_kfree(struct device *dev, void *p);
extern char *devm_kstrdup(struct device *dev, const char *s, gfp_t gfp);
extern void *devm_kmemdup(struct device *dev, const void *src, size_t len,
gfp_t gfp);
extern unsigned long devm_get_free_pages(struct device *dev,
gfp_t gfp_mask, unsigned int order);
extern void devm_free_pages(struct device *dev, unsigned long addr);
void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res);
void __iomem *devm_request_and_ioremap(struct device *dev,
@@ -673,6 +679,7 @@ struct acpi_dev_node {
* variants, which GPIO pins act in what additional roles, and so
* on. This shrinks the "Board Support Packages" (BSPs) and
* minimizes board-specific #ifdefs in drivers.
* @driver_data: Private pointer for driver specific info.
* @power: For device power management.
* See Documentation/power/devices.txt for details.
* @pm_domain: Provide callbacks that are executed during system suspend,
@@ -685,6 +692,7 @@ struct acpi_dev_node {
* @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
* hardware supports 64-bit addresses for consistent allocations
* such descriptors.
* @dma_pfn_offset: offset of DMA memory range relatively of RAM
* @dma_parms: A low level driver may set these to teach IOMMU code about
* segment limitations.
* @dma_pools: Dma pools (if dma'ble device).
@@ -734,6 +742,8 @@ struct device {
device */
void *platform_data; /* Platform specific data, device
core doesn't touch it */
void *driver_data; /* Driver data, set and get with
dev_set/get_drvdata */
struct dev_pm_info power;
struct dev_pm_domain *pm_domain;
@@ -750,6 +760,7 @@ struct device {
not all hardware supports
64 bit addresses for consistent
allocations such descriptors. */
unsigned long dma_pfn_offset;
struct device_dma_parameters *dma_parms;
@@ -823,6 +834,16 @@ static inline void set_dev_node(struct device *dev, int node)
}
#endif
static inline void *dev_get_drvdata(const struct device *dev)
{
return dev->driver_data;
}
static inline void dev_set_drvdata(struct device *dev, void *data)
{
dev->driver_data = data;
}
static inline struct pm_subsys_data *dev_to_psd(struct device *dev)
{
return dev ? dev->power.subsys_data : NULL;
@@ -907,8 +928,6 @@ extern int device_move(struct device *dev, struct device *new_parent,
extern const char *device_get_devnode(struct device *dev,
umode_t *mode, kuid_t *uid, kgid_t *gid,
const char **tmp);
extern void *dev_get_drvdata(const struct device *dev);
extern int dev_set_drvdata(struct device *dev, void *data);
static inline bool device_supports_offline(struct device *dev)
{

9
include/linux/dma-contiguous.h
View File

@@ -88,7 +88,8 @@ static inline void dma_contiguous_set_default(struct cma *cma)
void dma_contiguous_reserve(phys_addr_t addr_limit);
int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
phys_addr_t limit, struct cma **res_cma);
phys_addr_t limit, struct cma **res_cma,
bool fixed);
/**
* dma_declare_contiguous() - reserve area for contiguous memory handling
@@ -108,7 +109,7 @@ static inline int dma_declare_contiguous(struct device *dev, phys_addr_t size,
{
struct cma *cma;
int ret;
ret = dma_contiguous_reserve_area(size, base, limit, &cma);
ret = dma_contiguous_reserve_area(size, base, limit, &cma, true);
if (ret == 0)
dev_set_cma_area(dev, cma);
@@ -136,7 +137,9 @@ static inline void dma_contiguous_set_default(struct cma *cma) { }
static inline void dma_contiguous_reserve(phys_addr_t limit) { }
static inline int dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
phys_addr_t limit, struct cma **res_cma) {
phys_addr_t limit, struct cma **res_cma,
bool fixed)
{
return -ENOSYS;
}

20
include/linux/dma-mapping.h
View File

@@ -8,6 +8,12 @@
#include <linux/dma-direction.h>
#include <linux/scatterlist.h>
/*
* A dma_addr_t can hold any valid DMA or bus address for the platform.
* It can be given to a device to use as a DMA source or target. A CPU cannot
* reference a dma_addr_t directly because there may be translation between
* its physical address space and the bus address space.
*/
struct dma_map_ops {
void* (*alloc)(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t gfp,
@@ -123,6 +129,13 @@ static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
extern u64 dma_get_required_mask(struct device *dev);
#ifndef set_arch_dma_coherent_ops
static inline int set_arch_dma_coherent_ops(struct device *dev)
{
return 0;
}
#endif
static inline unsigned int dma_get_max_seg_size(struct device *dev)
{
return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
@@ -186,7 +199,7 @@ static inline int dma_get_cache_alignment(void)
#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
dma_addr_t device_addr, size_t size, int flags)
{
return 0;
@@ -217,13 +230,14 @@ extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
extern int dmam_declare_coherent_memory(struct device *dev,
phys_addr_t phys_addr,
dma_addr_t device_addr, size_t size,
int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
dma_addr_t bus_addr, dma_addr_t device_addr,
phys_addr_t phys_addr, dma_addr_t device_addr,
size_t size, gfp_t gfp)
{
return 0;

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